[U-Boot] [PATCH 4/5][v8] arch: powerpc: Move CONFIG_FSL_ELBC to Kconfig
Prabhakar Kushwaha
prabhakar.kushwaha at nxp.com
Thu Feb 2 09:31:48 UTC 2017
Enable ELBC from Kconfig.
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha at nxp.com>
---
Changes for v5: Added first time in the patch set
Changes for v6: Sending as it is
Changes for v7: Fix compiliation error
Changes for v8: Fix compiliation for ids8313
arch/powerpc/cpu/mpc85xx/Kconfig | 20 ++++++++++++++++++++
include/configs/MPC8536DS.h | 1 -
include/configs/MPC8569MDS.h | 2 --
include/configs/MPC8572DS.h | 1 -
include/configs/P1022DS.h | 1 -
include/configs/P1023RDB.h | 1 -
include/configs/P2041RDB.h | 1 -
include/configs/UCP1020.h | 1 -
include/configs/controlcenterd.h | 1 -
include/configs/corenet_ds.h | 1 -
include/configs/cyrus.h | 1 -
include/configs/km/kmp204x-common.h | 1 -
include/configs/p1_p2_rdb_pc.h | 1 -
include/configs/p1_twr.h | 1 -
include/configs/xpedite537x.h | 1 -
include/configs/xpedite550x.h | 1 -
16 files changed, 20 insertions(+), 16 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 83df733..c06a4db 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -455,6 +455,7 @@ config ARCH_MPC8536
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_2
select SYS_PPC_E500_USE_DEBUG_TLB
+ select FSL_ELBC
config ARCH_MPC8540
bool
@@ -478,6 +479,7 @@ config ARCH_MPC8544
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_2
select SYS_PPC_E500_USE_DEBUG_TLB
+ select FSL_ELBC
config ARCH_MPC8548
bool
@@ -524,6 +526,7 @@ config ARCH_MPC8569
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_2
+ select FSL_ELBC
config ARCH_MPC8572
bool
@@ -538,6 +541,7 @@ config ARCH_MPC8572
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_2
select SYS_PPC_E500_USE_DEBUG_TLB
+ select FSL_ELBC
config ARCH_P1010
bool
@@ -572,6 +576,7 @@ config ARCH_P1011
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_2
select SYS_PPC_E500_USE_DEBUG_TLB
+ select FSL_ELBC
config ARCH_P1020
bool
@@ -585,6 +590,7 @@ config ARCH_P1020
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_2
select SYS_PPC_E500_USE_DEBUG_TLB
+ select FSL_ELBC
config ARCH_P1021
bool
@@ -598,6 +604,7 @@ config ARCH_P1021
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_2
select SYS_PPC_E500_USE_DEBUG_TLB
+ select FSL_ELBC
config ARCH_P1022
bool
@@ -613,6 +620,7 @@ config ARCH_P1022
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_2
select SYS_PPC_E500_USE_DEBUG_TLB
+ select FSL_ELBC
config ARCH_P1023
bool
@@ -624,6 +632,7 @@ config ARCH_P1023
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
+ select FSL_ELBC
config ARCH_P1024
bool
@@ -637,6 +646,7 @@ config ARCH_P1024
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_2
select SYS_PPC_E500_USE_DEBUG_TLB
+ select FSL_ELBC
config ARCH_P1025
bool
@@ -650,6 +660,7 @@ config ARCH_P1025
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_2
select SYS_PPC_E500_USE_DEBUG_TLB
+ select FSL_ELBC
config ARCH_P2020
bool
@@ -664,6 +675,7 @@ config ARCH_P2020
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_2
select SYS_PPC_E500_USE_DEBUG_TLB
+ select FSL_ELBC
config ARCH_P2041
bool
@@ -685,6 +697,7 @@ config ARCH_P2041
select SYS_FSL_QORIQ_CHASSIS1
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
+ select FSL_ELBC
config ARCH_P3041
bool
@@ -708,6 +721,7 @@ config ARCH_P3041
select SYS_FSL_QORIQ_CHASSIS1
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
+ select FSL_ELBC
config ARCH_P4080
bool
@@ -742,6 +756,7 @@ config ARCH_P4080
select SYS_FSL_QORIQ_CHASSIS1
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
+ select FSL_ELBC
config ARCH_P5020
bool
@@ -762,6 +777,7 @@ config ARCH_P5020
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
select SYS_PPC64
+ select FSL_ELBC
config ARCH_P5040
bool
@@ -782,6 +798,7 @@ config ARCH_P5040
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
select SYS_PPC64
+ select FSL_ELBC
config ARCH_QEMU_E500
bool
@@ -1277,6 +1294,9 @@ config SYS_PPC_E500_USE_DEBUG_TLB
config FSL_IFC
bool
+config FSL_ELBC
+ bool
+
config SYS_PPC_E500_DEBUG_TLB
int "Temporary TLB entry for external debugger"
depends on SYS_PPC_E500_USE_DEBUG_TLB
diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h
index bc703ce..2267771 100644
--- a/include/configs/MPC8536DS.h
+++ b/include/configs/MPC8536DS.h
@@ -37,7 +37,6 @@
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#endif
-#define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */
#define CONFIG_PCI1 1 /* Enable PCI controller 1 */
#define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */
#define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */
diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h
index 2b0d98b..5cec847 100644
--- a/include/configs/MPC8569MDS.h
+++ b/include/configs/MPC8569MDS.h
@@ -10,8 +10,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_FSL_ELBC 1 /* Has Enhance localbus controller */
-
#define CONFIG_SYS_SRIO
#define CONFIG_SRIO1 /* SRIO port 1 */
diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h
index b933d21..3d4c8a8 100644
--- a/include/configs/MPC8572DS.h
+++ b/include/configs/MPC8572DS.h
@@ -28,7 +28,6 @@
/* High Level Configuration Options */
#define CONFIG_MP 1 /* support multiple processors */
-#define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */
#define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */
#define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */
#define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */
diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h
index 89eec12..04b0682 100644
--- a/include/configs/P1022DS.h
+++ b/include/configs/P1022DS.h
@@ -96,7 +96,6 @@
#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
#endif
-#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
#define CONFIG_PCIE3 /* PCIE controller 3 (ULI bridge) */
diff --git a/include/configs/P1023RDB.h b/include/configs/P1023RDB.h
index 1369035..58a3507 100644
--- a/include/configs/P1023RDB.h
+++ b/include/configs/P1023RDB.h
@@ -25,7 +25,6 @@
/* High Level Configuration Options */
#define CONFIG_MP /* support multiple processors */
-#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h
index f58fda1..1c3f43c 100644
--- a/include/configs/P2041RDB.h
+++ b/include/configs/P2041RDB.h
@@ -41,7 +41,6 @@
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
-#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
#define CONFIG_PCIE1 /* PCIE controller 1 */
#define CONFIG_PCIE2 /* PCIE controller 2 */
diff --git a/include/configs/UCP1020.h b/include/configs/UCP1020.h
index ad1a387..5f34a6d 100644
--- a/include/configs/UCP1020.h
+++ b/include/configs/UCP1020.h
@@ -14,7 +14,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_FSL_ELBC
#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
diff --git a/include/configs/controlcenterd.h b/include/configs/controlcenterd.h
index b1d67b2..666e8c6 100644
--- a/include/configs/controlcenterd.h
+++ b/include/configs/controlcenterd.h
@@ -137,7 +137,6 @@
/*
* Local Bus Definitions
*/
-#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
#define CONFIG_SYS_ELBC_BASE 0xe0000000
#ifdef CONFIG_PHYS_64BIT
diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
index 0f48f38..9b0afd7 100644
--- a/include/configs/corenet_ds.h
+++ b/include/configs/corenet_ds.h
@@ -59,7 +59,6 @@
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
-#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
#define CONFIG_PCIE1 /* PCIE controller 1 */
#define CONFIG_PCIE2 /* PCIE controller 2 */
diff --git a/include/configs/cyrus.h b/include/configs/cyrus.h
index 18a9156..2069346 100644
--- a/include/configs/cyrus.h
+++ b/include/configs/cyrus.h
@@ -49,7 +49,6 @@
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
-#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
#define CONFIG_PCIE1 /* PCIE controller 1 */
#define CONFIG_PCIE2 /* PCIE controller 2 */
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
diff --git a/include/configs/km/kmp204x-common.h b/include/configs/km/kmp204x-common.h
index 8669fcd..efd3b28 100644
--- a/include/configs/km/kmp204x-common.h
+++ b/include/configs/km/kmp204x-common.h
@@ -35,7 +35,6 @@
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
-#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
#define CONFIG_PCIE1 /* PCIE controller 1 */
#define CONFIG_PCIE3 /* PCIE controller 3 */
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index 5d70878..e376240 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -260,7 +260,6 @@
#define CONFIG_MP
-#define CONFIG_FSL_ELBC
#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
diff --git a/include/configs/p1_twr.h b/include/configs/p1_twr.h
index 52c544c..1ae7cf8 100644
--- a/include/configs/p1_twr.h
+++ b/include/configs/p1_twr.h
@@ -40,7 +40,6 @@
#define CONFIG_MP
-#define CONFIG_FSL_ELBC
#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
diff --git a/include/configs/xpedite537x.h b/include/configs/xpedite537x.h
index 5d78560..2f133d2 100644
--- a/include/configs/xpedite537x.h
+++ b/include/configs/xpedite537x.h
@@ -29,7 +29,6 @@
#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
-#define CONFIG_FSL_ELBC 1
/*
* Multicore config
diff --git a/include/configs/xpedite550x.h b/include/configs/xpedite550x.h
index 6346f84..4ac25a6 100644
--- a/include/configs/xpedite550x.h
+++ b/include/configs/xpedite550x.h
@@ -30,7 +30,6 @@
#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
-#define CONFIG_FSL_ELBC 1
/*
* Multicore config
--
2.7.4
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