[U-Boot] [PATCH] arm: socfpga: set the mpuclk divider in the Altera group register
Marek Vasut
marex at denx.de
Sat Feb 4 21:41:44 UTC 2017
On 01/31/2017 07:33 PM, Dinh Nguyen wrote:
> The mpuclk register in the Altera group of the clock manager
> divides the mpu_clk that is generated from the C0 output of the main
> pll.
>
> Without this patch, the default value of the register is 1, so the mpuclk
> will always get divided by 2 if the correct value is not set. For example,
> on the Arria5 socdk board, the MPU clock is only 525 MHz, and it should be
> 1.05 GHz.
>
> Signed-off-by: Dinh Nguyen <dinguyen at kernel.org>
Reviewed-by: Marek Vasut <marex at denx.de>
That's real neat, does that mean we get up to twice as much performance?
> ---
> arch/arm/mach-socfpga/clock_manager.c | 3 +++
> arch/arm/mach-socfpga/include/mach/clock_manager.h | 3 +++
> arch/arm/mach-socfpga/wrap_pll_config.c | 3 +++
> 3 files changed, 9 insertions(+)
>
> diff --git a/arch/arm/mach-socfpga/clock_manager.c b/arch/arm/mach-socfpga/clock_manager.c
> index aa71636..29e18f8 100644
> --- a/arch/arm/mach-socfpga/clock_manager.c
> +++ b/arch/arm/mach-socfpga/clock_manager.c
> @@ -167,6 +167,9 @@ void cm_basic_init(const struct cm_config * const cfg)
> /* main mpu */
> writel(cfg->mpuclk, &clock_manager_base->main_pll.mpuclk);
>
> + /* altera group mpuclk */
> + writel(cfg->altera_grp_mpuclk, &clock_manager_base->altera.mpuclk);
> +
> /* main main clock */
> writel(cfg->mainclk, &clock_manager_base->main_pll.mainclk);
>
> diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h b/arch/arm/mach-socfpga/include/mach/clock_manager.h
> index 2675951..803c926 100644
> --- a/arch/arm/mach-socfpga/include/mach/clock_manager.h
> +++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h
> @@ -55,6 +55,9 @@ struct cm_config {
> uint32_t ddr2xdqsclk;
> uint32_t ddrdqclk;
> uint32_t s2fuser2clk;
> +
> + /* altera group */
> + uint32_t altera_grp_mpuclk;
> };
>
> void cm_basic_init(const struct cm_config * const cfg);
> diff --git a/arch/arm/mach-socfpga/wrap_pll_config.c b/arch/arm/mach-socfpga/wrap_pll_config.c
> index 8a0a0e6..72b5f92 100644
> --- a/arch/arm/mach-socfpga/wrap_pll_config.c
> +++ b/arch/arm/mach-socfpga/wrap_pll_config.c
> @@ -116,6 +116,9 @@ static const struct cm_config cm_default_cfg = {
> CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_OFFSET) |
> (CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT <<
> CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_OFFSET),
> +
> + /* altera group */
> + CONFIG_HPS_ALTERAGRP_MPUCLK,
> };
>
> const struct cm_config * const cm_get_default_config(void)
>
--
Best regards,
Marek Vasut
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