[U-Boot] [PATCH] arm: socfpga: set the mpuclk divider in the Altera group register

[Marek Vasut]

On 02/08/2017 06:59 PM, Dinh Nguyen wrote:
> 
> 
> On 02/07/2017 07:32 PM, Marek Vasut wrote:
>> On 02/08/2017 02:21 AM, Marek Vasut wrote:
>>> On 01/31/2017 07:33 PM, Dinh Nguyen wrote:
>>>> The mpuclk register in the Altera group of the clock manager
>>>> divides the mpu_clk that is generated from the C0 output of the main
>>>> pll.
>>>>
>>>> Without this patch, the default value of the register is 1, so the mpuclk
>>>> will always get divided by 2 if the correct value is not set. For example,
>>>> on the Arria5 socdk board, the MPU clock is only 525 MHz, and it should be
>>>> 1.05 GHz.
>>>
>>> Applied to u-boot-socfpga/next (so for 2017.05), as the MW is closed and
>>> I'd rather be a bit careful here. Is my assumption correct that
>>> until now, the performance of the CPU in both C/V and A/V was halved?
>>
>> Hm in fact, it is already zero on C/V (I just checked) , so this seems
>> to be A/V specific ?
> 
> Yes, that's correct. It's A/V specific. But patch is good for all C/V as
> well. For the C/V devices, it numerator for the MPU clock is higher, so
> dividing by 2 put the mpuclk ~1GHz. But for A/V, dividing by 2 puts the
> clock at 525MHz. Pretty slow.

Cool, thanks for confirming. Maybe I should get it into 2017.03 release?
What do you think ?

-- 
Best regards,
Marek Vasut