[U-Boot] [PATCH v1 08/11] sun8i_emac: update to work with pinctrl-sunxi, reset-sunxi and clk-sunxi

Philipp Tomsich philipp.tomsich at theobroma-systems.com
Fri Feb 17 17:52:45 UTC 2017


parse_phy_pins() is parsing the pinctrl-entry of the emac-node, which
is in conflict with the new DM pinctrl driver for sun50i.  So when
building for sun50i and if the pinctrl driver is active, let the
parse_phy_pins()-function do nothing.

Use the DM reset and DM clk frameworks for getting the emac module out
of reset and enabling the clock gates.

Signed-off-by: Philipp Tomsich <philipp.tomsich at theobroma-systems.com>
---
 drivers/net/sun8i_emac.c | 45 +++++++++++++++++++++++++++++++++++++++++----
 1 file changed, 41 insertions(+), 4 deletions(-)

diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c
index 664d585..9d783e1 100644
--- a/drivers/net/sun8i_emac.c
+++ b/drivers/net/sun8i_emac.c
@@ -1,101 +1,107 @@
 /*
  * (C) Copyright 2016
  * Author: Amit Singh Tomar, amittomer25 at gmail.com
  *
  * SPDX-License-Identifier:     GPL-2.0+
  *
  * Ethernet driver for H3/A64/A83T based SoC's
  *
  * It is derived from the work done by
  * LABBE Corentin & Chen-Yu Tsai for Linux, THANKS!
  *
 */
 
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/gpio.h>
+#if defined(CONFIG_DM_GPIO)
+#include <asm-generic/gpio.h>
+#endif
+#if defined(CONFIG_CLK)
+#include <clk.h>
+#endif
 #include <common.h>
 #include <dm.h>
 #include <fdt_support.h>
 #include <linux/err.h>
 #include <malloc.h>
 #include <miiphy.h>
 #include <net.h>
-#ifdef CONFIG_DM_GPIO
-#include <asm-generic/gpio.h>
+#if defined(CONFIG_DM_RESET)
+#include <reset.h>
 #endif
 
 #define MDIO_CMD_MII_BUSY		BIT(0)
 #define MDIO_CMD_MII_WRITE		BIT(1)
 
 #define MDIO_CMD_MII_PHY_REG_ADDR_MASK	0x000001f0
 #define MDIO_CMD_MII_PHY_REG_ADDR_SHIFT	4
 #define MDIO_CMD_MII_PHY_ADDR_MASK	0x0001f000
 #define MDIO_CMD_MII_PHY_ADDR_SHIFT	12
 
 #define MDIO_CMD_MDC_DIV_RATIO_M_SHIFT  20
 #define MDIO_CMD_MDC_DIV_16             (0 << MDIO_CMD_MDC_DIV_RATIO_M_SHIFT)
 #define MDIO_CMD_MDC_DIV_32             (1 << MDIO_CMD_MDC_DIV_RATIO_M_SHIFT)
 #define MDIO_CMD_MDC_DIV_64             (2 << MDIO_CMD_MDC_DIV_RATIO_M_SHIFT)
 #define MDIO_CMD_MDC_DIV_128            (3 << MDIO_CMD_MDC_DIV_RATIO_M_SHIFT)
 
 #define CONFIG_TX_DESCR_NUM	32
 #define CONFIG_RX_DESCR_NUM	32
 #define CONFIG_ETH_BUFSIZE	2048 /* Note must be dma aligned */
 
 /*
  * The datasheet says that each descriptor can transfers up to 4096 bytes
  * But later, the register documentation reduces that value to 2048,
  * using 2048 cause strange behaviours and even BSP driver use 2047
  */
 #define CONFIG_ETH_RXSIZE	2044 /* Note must fit in ETH_BUFSIZE */
 
 #define TX_TOTAL_BUFSIZE	(CONFIG_ETH_BUFSIZE * CONFIG_TX_DESCR_NUM)
 #define RX_TOTAL_BUFSIZE	(CONFIG_ETH_BUFSIZE * CONFIG_RX_DESCR_NUM)
 
 #define H3_EPHY_DEFAULT_VALUE	0x58000
 #define H3_EPHY_DEFAULT_MASK	GENMASK(31, 15)
 #define H3_EPHY_ADDR_SHIFT	20
 #define REG_PHY_ADDR_MASK	GENMASK(4, 0)
 #define H3_EPHY_LED_POL		BIT(17)	/* 1: active low, 0: active high */
 #define H3_EPHY_SHUTDOWN	BIT(16)	/* 1: shutdown, 0: power up */
 #define H3_EPHY_SELECT		BIT(15) /* 1: internal PHY, 0: external PHY */
 
 #define SC_RMII_EN		BIT(13)
 #define SC_EPIT			BIT(2) /* 1: RGMII, 0: MII */
 #define SC_ETCS_MASK		GENMASK(1, 0)
 #define SC_ETCS_EXT_GMII	0x1
 #define SC_ETCS_INT_GMII	0x2
 
 #define CONFIG_MDIO_TIMEOUT	(3 * CONFIG_SYS_HZ)
 
 #define AHB_GATE_OFFSET_EPHY	0
 
 #if defined(CONFIG_MACH_SUN8I_H3)
 #define SUN8I_GPD8_GMAC		2
 #else
 #define SUN8I_GPD8_GMAC		4
 #endif
 
 /* H3/A64 EMAC Register's offset */
 #define EMAC_CTL0		0x00
 #define EMAC_CTL1		0x04
 #define EMAC_INT_STA		0x08
 #define EMAC_INT_EN		0x0c
 #define EMAC_TX_CTL0		0x10
 #define EMAC_TX_CTL1		0x14
 #define EMAC_TX_FLOW_CTL	0x1c
 #define EMAC_TX_DMA_DESC	0x20
 #define EMAC_RX_CTL0		0x24
 #define EMAC_RX_CTL1		0x28
 #define EMAC_RX_DMA_DESC	0x34
 #define EMAC_MII_CMD		0x48
 #define EMAC_MII_DATA		0x4c
 #define EMAC_ADDR0_HIGH		0x50
 #define EMAC_ADDR0_LOW		0x54
 #define EMAC_TX_DMA_STA		0xb0
 #define EMAC_TX_CUR_DESC	0xb4
 #define EMAC_TX_CUR_BUF		0xb8
 #define EMAC_RX_DMA_STA		0xc0
 #define EMAC_RX_CUR_DESC	0xc4
 
@@ -117,29 +123,35 @@ struct emac_dma_desc {
 struct emac_eth_dev {
 	struct emac_dma_desc rx_chain[CONFIG_TX_DESCR_NUM];
 	struct emac_dma_desc tx_chain[CONFIG_RX_DESCR_NUM];
 	char rxbuffer[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
 	char txbuffer[TX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
 
 	u32 interface;
 	u32 phyaddr;
 	u32 link;
 	u32 speed;
 	u32 duplex;
 	u32 phy_configured;
 	u32 tx_currdescnum;
 	u32 rx_currdescnum;
 	u32 addr;
 	u32 tx_slot;
 	bool use_internal_phy;
 
 	enum emac_variant variant;
 	void *mac_reg;
 	phys_addr_t sysctl_reg;
 	struct phy_device *phydev;
 	struct mii_dev *bus;
 #ifdef CONFIG_DM_GPIO
 	struct gpio_desc reset_gpio;
 #endif
+#ifdef CONFIG_DM_RESET
+	struct reset_ctl reset;
+#endif
+#ifdef CONFIG_CLK
+	struct clk ahb_clk_gate;
+#endif
 };
 
 
@@ -459,45 +471,47 @@ static int _sun8i_emac_eth_init(struct emac_eth_dev *priv, u8 *enetaddr)
 
 static int parse_phy_pins(struct udevice *dev)
 {
+#if !(defined(CONFIG_MACH_SUN50I) && defined(CONFIG_SUNXI_PINCTRL))
 	int offset;
 	const char *pin_name;
 	int drive, pull, i;
 
 	offset = fdtdec_lookup_phandle(gd->fdt_blob, dev_of_offset(dev),
 				       "pinctrl-0");
 	if (offset < 0) {
 		printf("WARNING: emac: cannot find pinctrl-0 node\n");
 		return offset;
 	}
 
 	drive = fdt_getprop_u32_default_node(gd->fdt_blob, offset, 0,
 					     "allwinner,drive", 4);
 	pull = fdt_getprop_u32_default_node(gd->fdt_blob, offset, 0,
 					    "allwinner,pull", 0);
 	for (i = 0; ; i++) {
 		int pin;
 
 		pin_name = fdt_stringlist_get(gd->fdt_blob, offset,
 					      "allwinner,pins", i, NULL);
 		if (!pin_name)
 			break;
 		if (pin_name[0] != 'P')
 			continue;
 		pin = (pin_name[1] - 'A') << 5;
 		if (pin >= 26 << 5)
 			continue;
 		pin += simple_strtol(&pin_name[2], NULL, 10);
 
 		sunxi_gpio_set_cfgpin(pin, SUN8I_GPD8_GMAC);
 		sunxi_gpio_set_drv(pin, drive);
 		sunxi_gpio_set_pull(pin, pull);
 	}
 
 	if (!i) {
 		printf("WARNING: emac: cannot find allwinner,pins property\n");
 		return -2;
 	}
+#endif
 
 	return 0;
 }
 
@@ -609,20 +623,28 @@ static int sun8i_eth_write_hwaddr(struct udevice *dev)
 static void sun8i_emac_board_setup(struct emac_eth_dev *priv)
 {
 	struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 
 	if (priv->use_internal_phy) {
 		/* Set clock gating for ephy */
 		setbits_le32(&ccm->bus_gate4, BIT(AHB_GATE_OFFSET_EPHY));
 
 		/* Deassert EPHY */
 		setbits_le32(&ccm->ahb_reset2_cfg, BIT(AHB_RESET_OFFSET_EPHY));
 	}
 
 	/* Set clock gating for emac */
+#if defined(CONFIG_CLK)
+	clk_enable(&priv->ahb_clk_gate);
+#else
 	setbits_le32(&ccm->ahb_gate0, BIT(AHB_GATE_OFFSET_GMAC));
+#endif
 
 	/* De-assert EMAC */
+#if defined(CONFIG_DM_RESET)
+	reset_deassert(&priv->reset);
+#else
 	setbits_le32(&ccm->ahb_reset0_cfg, BIT(AHB_RESET_OFFSET_GMAC));
+#endif
 }
 
 #if defined(CONFIG_DM_GPIO)
@@ -772,75 +794,90 @@ static const struct eth_ops sun8i_emac_eth_ops = {
 static int sun8i_emac_eth_ofdata_to_platdata(struct udevice *dev)
 {
 	struct sun8i_eth_pdata *sun8i_pdata = dev_get_platdata(dev);
 	struct eth_pdata *pdata = &sun8i_pdata->eth_pdata;
 	struct emac_eth_dev *priv = dev_get_priv(dev);
 	const char *phy_mode;
 	int node = dev_of_offset(dev);
 	int offset = 0;
 #ifdef CONFIG_DM_GPIO
 	int reset_flags = GPIOD_IS_OUT;
 	int ret = 0;
 #endif
 
 	pdata->iobase = dev_get_addr_name(dev, "emac");
 	priv->sysctl_reg = dev_get_addr_name(dev, "syscon");
 
 	pdata->phy_interface = -1;
 	priv->phyaddr = -1;
 	priv->use_internal_phy = false;
 
 	offset = fdtdec_lookup_phandle(gd->fdt_blob, node,
 				       "phy");
 	if (offset > 0)
 		priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg",
 					       -1);
 
 	phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL);
 
 	if (phy_mode)
 		pdata->phy_interface = phy_get_interface_by_name(phy_mode);
 	printf("phy interface%d\n", pdata->phy_interface);
 
 	if (pdata->phy_interface == -1) {
 		debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
 		return -EINVAL;
 	}
 
 	priv->variant = dev_get_driver_data(dev);
 
 	if (!priv->variant) {
 		printf("%s: Missing variant '%s'\n", __func__,
 		       (char *)priv->variant);
 		return -EINVAL;
 	}
 
 	if (priv->variant == H3_EMAC) {
 		if (fdt_getprop(gd->fdt_blob, node,
 				"allwinner,use-internal-phy", NULL))
 			priv->use_internal_phy = true;
 	}
 
 	priv->interface = pdata->phy_interface;
 
 	if (!priv->use_internal_phy)
 		parse_phy_pins(dev);
 
-#ifdef CONFIG_DM_GPIO
+#if defined(CONFIG_DM_GPIO)
 	if (fdtdec_get_bool(gd->fdt_blob, dev->of_offset,
 			    "allwinner,reset-active-low"))
 		reset_flags |= GPIOD_ACTIVE_LOW;
 
 	ret = gpio_request_by_name(dev, "allwinner,reset-gpio", 0,
 				   &priv->reset_gpio, reset_flags);
 
 	if (ret == 0) {
 		ret = fdtdec_get_int_array(gd->fdt_blob, dev->of_offset,
-					   "allwinner,reset-delays-us", sun8i_pdata->reset_delays, 3);
+					   "allwinner,reset-delays-us",
+					   sun8i_pdata->reset_delays, 3);
 	} else if (ret == -ENOENT) {
 		ret = 0;
 	}
 #endif
 
+#if defined(CONFIG_DM_RESET)
+	if (reset_get_by_name(dev, "ahb", &priv->reset)) {
+		error("%s: failed to get 'ahb' reset\n", dev->name);
+		return -EINVAL;
+	}
+#endif
+
+#if defined(CONFIG_CLK)
+	if (clk_get_by_name(dev, "ahb", &priv->ahb_clk_gate)) {
+		error("%s: failed to get 'ahb' clock\n", dev->name);
+		return -EINVAL;
+	}
+#endif
+
 	return 0;
 }
 
-- 
1.9.1



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