[U-Boot] [PATCH] arm: socfpga: Add support for the Terasic DE10-nano

Sun Feb 19 02:25:53 UTC 2017

On 02/19/2017 01:59 AM, Dalon Westergreen wrote:
> On Sun, 2017-02-19 at 01:35 +0100, Marek Vasut wrote:
>> On 02/19/2017 12:15 AM, Dalon Westergreen wrote:
>>>
>>> On Sat, 2017-02-18 at 22:04 +0100, Marek Vasut wrote:
>>>>
>>>> On 02/18/2017 09:56 PM, Dalon Westergreen wrote:
>>>>>
>>>>>
>>>>> Add support for the cyclone5 soc based Terasic DE10-nano.  The
>>>>> board is a second generation version of the DE0-nano-soc but has
>>>>> the a larger FPGA and hdmi support.
>>>>>
>>>>> Signed-off-by: Dalon Westergreen <dwesterg at gmail.com>
>>>>
>>>> Looks pretty nice, minor nits below
>>>>
>>>> [...]
>>>>
>>>>>
>>>>>
>>>>> diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-
>>>>> socfpga/Kconfig
>>>>> index e56b3db..6a776b5 100644
>>>>> --- a/arch/arm/mach-socfpga/Kconfig
>>>>> +++ b/arch/arm/mach-socfpga/Kconfig
>>>>> @@ -85,6 +85,10 @@ config TARGET_SOCFPGA_TERASIC_DE1_SOC
>>>>>  	bool "Terasic DE1-SoC (Cyclone V)"
>>>>>  	select TARGET_SOCFPGA_CYCLONE5
>>>>>  
>>>>> +config TARGET_SOCFPGA_TERASIC_DE10_NANO
>>>>> +	bool "Terasic DE10-Nano (Cyclone V)"
>>>>> +	select TARGET_SOCFPGA_CYCLONE5
>>>>> +
>>>>>  config TARGET_SOCFPGA_TERASIC_SOCKIT
>>>>>  	bool "Terasic SoCkit (Cyclone V)"
>>>>>  	select TARGET_SOCFPGA_CYCLONE5
>>>>> @@ -96,6 +100,7 @@ config SYS_BOARD
>>>>>  	default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
>>>>>  	default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
>>>>>  	default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
>>>>> +	default "de10-nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
>>>>>  	default "is1" if TARGET_SOCFPGA_IS1
>>>>>  	default "mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
>>>>>  	default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
>>>>> @@ -112,6 +117,7 @@ config SYS_VENDOR
>>>>>  	default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
>>>>>  	default "terasic" if TARGET_SOCFPGA_TERASIC_DE1_SOC
>>>>>  	default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
>>>>> +	default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_NANO
>>>>
>>>> Keep the list sorted please.
>>>>
>>>>>
>>>>>
>>>>>  
>>>>>  config SYS_SOC
>>>>>  	default "socfpga"
>>>>> @@ -121,6 +127,7 @@ config SYS_CONFIG_NAME
>>>>>  	default "socfpga_cyclone5_socdk" if
>>>>> TARGET_SOCFPGA_CYCLONE5_SOCDK
>>>>>  	default "socfpga_de0_nano_soc" if
>>>>> TARGET_SOCFPGA_TERASIC_DE0_NANO
>>>>>  	default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
>>>>> +	default "socfpga_de10_nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
>>>>>  	default "socfpga_is1" if TARGET_SOCFPGA_IS1
>>>>>  	default "socfpga_mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
>>>>>  	default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
>>>>> diff --git a/board/terasic/de10-nano/MAINTAINERS b/board/terasic/de10-
>>>>> nano/MAINTAINERS
>>>>> new file mode 100644
>>>>> index 0000000..f4dd0df
>>>>> --- /dev/null
>>>>> +++ b/board/terasic/de10-nano/MAINTAINERS
>>>>> @@ -0,0 +1,5 @@
>>>>> +DE10-NANO BOARD
>>>>> +M:	Dalon Westergreen <dwesterg at gmail.com>
>>>>> +S:	Maintained
>>>>> +F:	include/configs/socfpga_de10_nano.h
>>>>> +F:	configs/socfpga_de10_nano_defconfig
>>>>> diff --git a/board/terasic/de10-nano/Makefile b/board/terasic/de10-
>>>>> nano/Makefile
>>>>> new file mode 100644
>>>>> index 0000000..86f9b78
>>>>> --- /dev/null
>>>>> +++ b/board/terasic/de10-nano/Makefile
>>>>> @@ -0,0 +1,9 @@
>>>>> +#
>>>>> +# (C) Copyright 2001-2006
>>>>> +# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
>>>>> +# (C) Copyright 2010, Thomas Chou <thomas at wytron.com.tw>
>>>>
>>>> Really ? Looks like a new file, so (C) you
>>>>
>>>>>
>>>>>
>>>>> +# SPDX-License-Identifier:	GPL-2.0+
>>>>> +#
>>>>> +
>>>>> +obj-y	:= socfpga.o
>>>>
>>>> [...]
>>>>
>>>>>
>>>>>
>>>>> diff --git a/include/configs/socfpga_de10_nano.h
>>>>> b/include/configs/socfpga_de10_nano.h
>>>>> new file mode 100644
>>>>> index 0000000..61a5066
>>>>> --- /dev/null
>>>>> +++ b/include/configs/socfpga_de10_nano.h
>>>>> @@ -0,0 +1,36 @@
>>>>> +/*
>>>>> + * Copyright (C) 2017, Intel Corporation
>>>>> + *
>>>>> + * SPDX-License-Identifier:	GPL-2.0+
>>>>> + */
>>>>> +#ifndef __CONFIG_TERASIC_DE10_H__
>>>>> +#define __CONFIG_TERASIC_DE10_H__
>>>>> +
>>>>> +#include <asm/arch/base_addr_ac5.h>
>>>>> +
>>>>> +/* U-Boot Commands */
>>>>> +#define CONFIG_FAT_WRITE
>>>>> +#define CONFIG_HW_WATCHDOG
>>>>> +
>>>>> +/* Memory configurations */
>>>>> +#define PHYS_SDRAM_1_SIZE		0x40000000	/* 1GiB */
>>>>> +
>>>>> +/* Booting Linux */
>>>>> +#define CONFIG_BOOTFILE		"zImage"
>>>>> +#define CONFIG_LOADADDR		0x01000000
>>>>> +#define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
>>>>> +
>>>>> +/* Ethernet on SoC (EMAC) */
>>>>> +#if defined(CONFIG_CMD_NET)
>>>>> +#define CONFIG_PHY_MICREL
>>>>> +#define CONFIG_PHY_MICREL_KSZ9031
>>>>> +#endif
>>>>> +
>>>>> +#define CONFIG_ENV_IS_IN_MMC
>>>>> +
>>>>> +#define CONFIG_BOOTCOMMAND "run fpga_cfg; run distro_bootcmd"
>>>>
>>>> What is "fpga_cfg" ?
>>> sorry, thanks for catching that.  i am playing with something
>>> like the way distro boot searches for files, but for the fpga image.
>>
>> Like the FPGA manager which is being upstreamed into Linux and which is
>> the only sensible way to manage reprogramable hardware ? :) Also, if you
>> used fitImage instead of that stupid zImage, you would be able to bundle
>> all the components needed to boot system into a single consistent image ;-)
>>
> I know, that is my next step... :)
> 
Cool :)

-- 
Best regards,
Marek Vasut