[U-Boot] [PATCH 4/7] pinctrl: rockchip: add support for rk3328
Simon Glass
sjg at chromium.org
Tue Feb 21 18:06:56 UTC 2017
Hi Kever,
On 17 February 2017 at 01:07, Kever Yang <kever.yang at rock-chips.com> wrote:
> Add rk3328 pinctrl driver and grf/iomux structure definition.
>
> Signed-off-by: William Zhang <william.zhang at rock-chips.com>
> Signed-off-by: Kever Yang <kever.yang at rock-chips.com>
> ---
>
> arch/arm/include/asm/arch-rockchip/grf_rk3328.h | 134 ++++++++
> drivers/pinctrl/Kconfig | 9 +
> drivers/pinctrl/rockchip/Makefile | 1 +
> drivers/pinctrl/rockchip/pinctrl_rk3328.c | 418 ++++++++++++++++++++++++
> include/dt-bindings/pinctrl/rockchip.h | 2 +
> 5 files changed, 564 insertions(+)
> create mode 100644 arch/arm/include/asm/arch-rockchip/grf_rk3328.h
> create mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3328.c
Acked-by: Simon Glass <sjg at chromium.org>
Nits below.
[...]
In your clock structures, please add space around operators:
+ u32 reserved1[(0x100-0x54)/4];
[(0x100 - 0x54) / 4]
> diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3328.c b/drivers/pinctrl/rockchip/pinctrl_rk3328.c
> new file mode 100644
> index 0000000..3fa334f
> --- /dev/null
> +++ b/drivers/pinctrl/rockchip/pinctrl_rk3328.c
> @@ -0,0 +1,418 @@
> +/*
> + * (C) Copyright 2016 Rockchip Electronics Co., Ltd
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <asm/arch/clock.h>
> +#include <asm/arch/grf_rk3328.h>
> +#include <asm/arch/hardware.h>
> +#include <asm/arch/periph.h>
> +#include <asm/io.h>
> +#include <dm.h>
> +#include <dm/pinctrl.h>
> +#include <errno.h>
> +#include <syscon.h>
Please fix header order.
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +struct rk3328_pinctrl_priv {
> + struct rk3328_grf_regs *grf;
> +};
> +
> +enum {
> + /* GRF_GPIO0A_IOMUX */
> + GRF_GPIO0A5_SEL_SHIFT = 10,
> + GRF_GPIO0A5_SEL_MASK = 3 << GRF_GPIO0A5_SEL_SHIFT,
> + GRF_I2C3_SCL = 2,
> +
> + GRF_GPIO0A6_SEL_SHIFT = 12,
> + GRF_GPIO0A6_SEL_MASK = 3 << GRF_GPIO0A6_SEL_SHIFT,
> + GRF_I2C3_SDA = 2,
> +
> + GRF_GPIO0A7_SEL_SHIFT = 14,
> + GRF_GPIO0A7_SEL_MASK = 3 << GRF_GPIO0A7_SEL_SHIFT,
> + GRF_EMMC_DATA0 = 2,
> +
> + /* GRF_GPIO1A_IOMUX */
> + GRF_GPIO1A0_SEL_SHIFT = 0,
> + GRF_GPIO1A0_SEL_MASK = 0x3fff << GRF_GPIO1A0_SEL_SHIFT,
> + GRF_CARD_DATA_CLK_CMD_DETN = 0x1555,
> +
> + /* GRF_GPIO2A_IOMUX */
> + GRF_GPIO2A0_SEL_SHIFT = 0,
> + GRF_GPIO2A0_SEL_MASK = 3 << GRF_GPIO2A0_SEL_SHIFT,
> + GRF_UART2_TX_M1 = 1,
> +
> + GRF_GPIO2A1_SEL_SHIFT = 2,
> + GRF_GPIO2A1_SEL_MASK = 3 << GRF_GPIO2A1_SEL_SHIFT,
> + GRF_UART2_RX_M1 = 1,
> +
> + GRF_GPIO2A2_SEL_SHIFT = 4,
> + GRF_GPIO2A2_SEL_MASK = 3 << GRF_GPIO2A2_SEL_SHIFT,
> + GRF_PWM_IR = 1,
> +
> + GRF_GPIO2A4_SEL_SHIFT = 8,
> + GRF_GPIO2A4_SEL_MASK = 3 << GRF_GPIO2A4_SEL_SHIFT,
> + GRF_PWM_0 = 1,
> + GRF_I2C1_SDA,
> +
> + GRF_GPIO2A5_SEL_SHIFT = 10,
> + GRF_GPIO2A5_SEL_MASK = 3 << GRF_GPIO2A5_SEL_SHIFT,
> + GRF_PWM_1 = 1,
> + GRF_I2C1_SCL,
> +
> + GRF_GPIO2A6_SEL_SHIFT = 12,
> + GRF_GPIO2A6_SEL_MASK = 3 << GRF_GPIO2A6_SEL_SHIFT,
> + GRF_PWM_2 = 1,
> +
> + GRF_GPIO2A7_SEL_SHIFT = 14,
> + GRF_GPIO2A7_SEL_MASK = 3 << GRF_GPIO2A7_SEL_SHIFT,
> + GRF_CARD_PWR_EN_M0 = 1,
> +
> + /* GRF_GPIO2BL_IOMUX */
> + GRF_GPIO2BL0_SEL_SHIFT = 0,
> + GRF_GPIO2BL0_SEL_MASK = 0x3f << GRF_GPIO2BL0_SEL_SHIFT,
> + GRF_SPI_CLK_TX_RX_M0 = 0x15,
> +
> + GRF_GPIO2BL3_SEL_SHIFT = 6,
> + GRF_GPIO2BL3_SEL_MASK = 3 << GRF_GPIO2BL3_SEL_SHIFT,
> + GRF_SPI_CSN0_M0 = 1,
> +
> + GRF_GPIO2BL4_SEL_SHIFT = 8,
> + GRF_GPIO2BL4_SEL_MASK = 3 << GRF_GPIO2BL4_SEL_SHIFT,
> + GRF_SPI_CSN1_M0 = 1,
> +
> + GRF_GPIO2BL5_SEL_SHIFT = 10,
> + GRF_GPIO2BL5_SEL_MASK = 3 << GRF_GPIO2BL5_SEL_SHIFT,
> + GRF_I2C2_SDA = 1,
> +
> + GRF_GPIO2BL6_SEL_SHIFT = 12,
> + GRF_GPIO2BL6_SEL_MASK = 3 << GRF_GPIO2BL6_SEL_SHIFT,
> + GRF_I2C2_SCL = 1,
> +
> + /* GRF_GPIO2D_IOMUX */
> + GRF_GPIO2D0_SEL_SHIFT = 0,
> + GRF_GPIO2D0_SEL_MASK = 3 << GRF_GPIO2D0_SEL_SHIFT,
> + GRF_I2C0_SCL = 1,
> +
> + GRF_GPIO2D1_SEL_SHIFT = 2,
> + GRF_GPIO2D1_SEL_MASK = 3 << GRF_GPIO2D1_SEL_SHIFT,
> + GRF_I2C0_SDA = 1,
> +
> + GRF_GPIO2D4_SEL_SHIFT = 8,
> + GRF_GPIO2D4_SEL_MASK = 0xff << GRF_GPIO2D4_SEL_SHIFT,
> + GRF_EMMC_DATA123 = 0xaa,
> +
> + /* GRF_GPIO3C_IOMUX */
> + GRF_GPIO3C0_SEL_SHIFT = 0,
> + GRF_GPIO3C0_SEL_MASK = 0x3fff << GRF_GPIO3C0_SEL_SHIFT,
> + GRF_EMMC_DATA567_PWR_CLK_RSTN_CMD = 0x2aaa,
> +
> + /* GRF_COM_IOMUX */
> + GRF_UART2_IOMUX_SEL_SHIFT = 0,
> + GRF_UART2_IOMUX_SEL_MASK = 3 << GRF_UART2_IOMUX_SEL_SHIFT,
> + GRF_UART2_IOMUX_SEL_M0 = 0,
> + GRF_UART2_IOMUX_SEL_M1,
> +
> + GRF_SPI_IOMUX_SEL_SHIFT = 4,
> + GRF_SPI_IOMUX_SEL_MASK = 3 << GRF_SPI_IOMUX_SEL_SHIFT,
> + GRF_SPI_IOMUX_SEL_M0 = 0,
> + GRF_SPI_IOMUX_SEL_M1,
> + GRF_SPI_IOMUX_SEL_M2,
> +
> + GRF_CARD_IOMUX_SEL_SHIFT = 7,
> + GRF_CARD_IOMUX_SEL_MASK = 1 << GRF_CARD_IOMUX_SEL_SHIFT,
> + GRF_CARD_IOMUX_SEL_M0 = 0,
> + GRF_CARD_IOMUX_SEL_M1,
> +};
blank line here
> +static void pinctrl_rk3328_pwm_config(struct rk3328_grf_regs *grf, int pwm_id)
> +{
> + switch (pwm_id) {
> + case PERIPH_ID_PWM0:
> + rk_clrsetreg(&grf->gpio2a_iomux,
> + GRF_GPIO2A4_SEL_MASK,
> + GRF_PWM_0 << GRF_GPIO2A4_SEL_SHIFT);
> + break;
> + case PERIPH_ID_PWM1:
> + rk_clrsetreg(&grf->gpio2a_iomux,
> + GRF_GPIO2A5_SEL_MASK,
> + GRF_PWM_1 << GRF_GPIO2A5_SEL_SHIFT);
> + break;
> + case PERIPH_ID_PWM2:
> + rk_clrsetreg(&grf->gpio2a_iomux,
> + GRF_GPIO2A6_SEL_MASK,
> + GRF_PWM_2 << GRF_GPIO2A6_SEL_SHIFT);
> + break;
> + case PERIPH_ID_PWM3:
> + rk_clrsetreg(&grf->gpio2a_iomux,
> + GRF_GPIO2A2_SEL_MASK,
> + GRF_PWM_IR << GRF_GPIO2A2_SEL_SHIFT);
> + break;
> + default:
> + debug("pwm id = %d iomux error!\n", pwm_id);
> + break;
> + }
> +}
> +
Regards,
Simon
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