[U-Boot] [PATCH v2 3/7] rockchip: rk3288: add clock driver
Simon Glass
sjg at chromium.org
Thu Feb 23 03:35:38 UTC 2017
Hi Kever,
On 22 February 2017 at 03:13, Kever Yang <kever.yang at rock-chips.com> wrote:
> Add rk3328 clock driver and cru structure definition.
>
> Signed-off-by: William Zhang <william.zhang at rock-chips.com>
> Signed-off-by: Kever Yang <kever.yang at rock-chips.com>
> ---
>
> Changes in v2:
> - split rockchip_get_cru into arch/arm/mach-rockchip
> - fix include header file order
> - drop MACRO for I2C reg access
It looks like they are still here.
> - use OSC_HZ for 24*1024*1024
>
> arch/arm/include/asm/arch-rockchip/cru_rk3328.h | 70 +++
> arch/arm/mach-rockchip/rk3328/Makefile | 1 +
> arch/arm/mach-rockchip/rk3328/clk_rk3328.c | 31 ++
> drivers/clk/rockchip/Makefile | 1 +
> drivers/clk/rockchip/clk_rk3328.c | 597 ++++++++++++++++++++++++
> 5 files changed, 700 insertions(+)
> create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rk3328.h
> create mode 100644 arch/arm/mach-rockchip/rk3328/clk_rk3328.c
> create mode 100644 drivers/clk/rockchip/clk_rk3328.c
>
[..]
> diff --git a/drivers/clk/rockchip/clk_rk3328.c b/drivers/clk/rockchip/clk_rk3328.c
> new file mode 100644
> index 0000000..4428a80
> --- /dev/null
> +++ b/drivers/clk/rockchip/clk_rk3328.c
> @@ -0,0 +1,597 @@
> +/*
> + * (C) Copyright 2017 Rockchip Electronics Co., Ltd
> + *
> + * SPDX-License-Identifier: GPL-2.0
> + */
> +
[..]
> +#define I2C_CLK_REG_MASK(bus) \
> + (CLK_I2C_DIV_CON_MASK << \
> + CLK_I2C ##bus## _DIV_CON_SHIFT | \
> + CLK_I2C_PLL_SEL_MASK << \
> + CLK_I2C ##bus## _PLL_SEL_SHIFT)
> +
> +#define I2C_CLK_REG_VALUE(bus, clk_div) \
> + ((clk_div - 1) << \
> + CLK_I2C ##bus## _DIV_CON_SHIFT | \
> + CLK_I2C_PLL_SEL_GPLL << \
> + CLK_I2C ##bus## _PLL_SEL_SHIFT)
> +
> +#define I2C_CLK_DIV_VALUE(con, bus) \
> + (con >> CLK_I2C ##bus## _DIV_CON_SHIFT) & \
> + CLK_I2C_DIV_CON_MASK;
See above.
Regards,
Simon
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