[U-Boot] [PATCH V4 12/19] i2c: lpi2c: add lpi2c driver for i.MX7ULP
Peng Fan
peng.fan at nxp.com
Fri Feb 24 03:56:43 UTC 2017
Add lpi2c driver for i.MX7ULP.
Need to enable the two options to use this driver:
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_IMX_LPI2C=y
Signed-off-by: Peng Fan <peng.fan at nxp.com>
Acked-by: Heiko Schocher <hs at denx.de>
Cc: Stefano Babic <sbabic at denx.de>
---
I do not repost the whole patch set, only post the single lpi2c patch
in V4. Other patches are still valid in V3.
V4:
Use SYS_I2C_IMX_LPI2C as the Kconfig entry
Add Ack tag
V3:
none
V2:
none
arch/arm/include/asm/arch-mx7ulp/imx_lpi2c.h | 520 +++++++++++++++++++++++++++
drivers/i2c/Kconfig | 6 +
drivers/i2c/Makefile | 1 +
drivers/i2c/imx_lpi2c.c | 462 ++++++++++++++++++++++++
4 files changed, 989 insertions(+)
create mode 100644 arch/arm/include/asm/arch-mx7ulp/imx_lpi2c.h
create mode 100644 drivers/i2c/imx_lpi2c.c
diff --git a/arch/arm/include/asm/arch-mx7ulp/imx_lpi2c.h b/arch/arm/include/asm/arch-mx7ulp/imx_lpi2c.h
new file mode 100644
index 0000000..f1b3113
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx7ulp/imx_lpi2c.h
@@ -0,0 +1,520 @@
+/*
+ * Copyright 2016 Freescale Semiconductors, Inc.
+ *
+ * I2CLP driver for i.MX
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ */
+#ifndef __IMX_LPI2C_H__
+#define __IMX_LPI2C_H__
+
+struct imx_lpi2c_bus {
+ int index;
+ ulong base;
+ ulong driver_data;
+ int speed;
+ struct i2c_pads_info *pads_info;
+ struct udevice *bus;
+};
+
+struct imx_lpi2c_reg {
+ u32 verid;
+ u32 param;
+ u8 reserved_0[8];
+ u32 mcr;
+ u32 msr;
+ u32 mier;
+ u32 mder;
+ u32 mcfgr0;
+ u32 mcfgr1;
+ u32 mcfgr2;
+ u32 mcfgr3;
+ u8 reserved_1[16];
+ u32 mdmr;
+ u8 reserved_2[4];
+ u32 mccr0;
+ u8 reserved_3[4];
+ u32 mccr1;
+ u8 reserved_4[4];
+ u32 mfcr;
+ u32 mfsr;
+ u32 mtdr;
+ u8 reserved_5[12];
+ u32 mrdr;
+ u8 reserved_6[156];
+ u32 scr;
+ u32 ssr;
+ u32 sier;
+ u32 sder;
+ u8 reserved_7[4];
+ u32 scfgr1;
+ u32 scfgr2;
+ u8 reserved_8[20];
+ u32 samr;
+ u8 reserved_9[12];
+ u32 sasr;
+ u32 star;
+ u8 reserved_10[8];
+ u32 stdr;
+ u8 reserved_11[12];
+ u32 srdr;
+};
+
+typedef enum lpi2c_status {
+ LPI2C_SUCESS = 0,
+ LPI2C_END_PACKET_ERR,
+ LPI2C_STOP_ERR,
+ LPI2C_NAK_ERR,
+ LPI2C_ARB_LOST_ERR,
+ LPI2C_FIFO_ERR,
+ LPI2C_PIN_LOW_TIMEOUT_ERR,
+ LPI2C_DATA_MATCH_ERR,
+ LPI2C_BUSY,
+ LPI2C_IDLE,
+ LPI2C_BIT_ERR,
+ LPI2C_NO_TRANS_PROG,
+ LPI2C_DMA_REQ_FAIL,
+} lpi2c_status_t;
+
+/* ----------------------------------------------------------------------------
+ -- LPI2C Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPI2C_Register_Masks LPI2C Register Masks
+ * @{
+ */
+
+/*! @name VERID - Version ID Register */
+#define LPI2C_VERID_FEATURE_MASK (0xFFFFU)
+#define LPI2C_VERID_FEATURE_SHIFT (0U)
+#define LPI2C_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_FEATURE_SHIFT)) & LPI2C_VERID_FEATURE_MASK)
+#define LPI2C_VERID_MINOR_MASK (0xFF0000U)
+#define LPI2C_VERID_MINOR_SHIFT (16U)
+#define LPI2C_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MINOR_SHIFT)) & LPI2C_VERID_MINOR_MASK)
+#define LPI2C_VERID_MAJOR_MASK (0xFF000000U)
+#define LPI2C_VERID_MAJOR_SHIFT (24U)
+#define LPI2C_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MAJOR_SHIFT)) & LPI2C_VERID_MAJOR_MASK)
+
+/*! @name PARAM - Parameter Register */
+#define LPI2C_PARAM_MTXFIFO_MASK (0xFU)
+#define LPI2C_PARAM_MTXFIFO_SHIFT (0U)
+#define LPI2C_PARAM_MTXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MTXFIFO_SHIFT)) & LPI2C_PARAM_MTXFIFO_MASK)
+#define LPI2C_PARAM_MRXFIFO_MASK (0xF00U)
+#define LPI2C_PARAM_MRXFIFO_SHIFT (8U)
+#define LPI2C_PARAM_MRXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MRXFIFO_SHIFT)) & LPI2C_PARAM_MRXFIFO_MASK)
+
+/*! @name MCR - Master Control Register */
+#define LPI2C_MCR_MEN_MASK (0x1U)
+#define LPI2C_MCR_MEN_SHIFT (0U)
+#define LPI2C_MCR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_MEN_SHIFT)) & LPI2C_MCR_MEN_MASK)
+#define LPI2C_MCR_RST_MASK (0x2U)
+#define LPI2C_MCR_RST_SHIFT (1U)
+#define LPI2C_MCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RST_SHIFT)) & LPI2C_MCR_RST_MASK)
+#define LPI2C_MCR_DOZEN_MASK (0x4U)
+#define LPI2C_MCR_DOZEN_SHIFT (2U)
+#define LPI2C_MCR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DOZEN_SHIFT)) & LPI2C_MCR_DOZEN_MASK)
+#define LPI2C_MCR_DBGEN_MASK (0x8U)
+#define LPI2C_MCR_DBGEN_SHIFT (3U)
+#define LPI2C_MCR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DBGEN_SHIFT)) & LPI2C_MCR_DBGEN_MASK)
+#define LPI2C_MCR_RTF_MASK (0x100U)
+#define LPI2C_MCR_RTF_SHIFT (8U)
+#define LPI2C_MCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RTF_SHIFT)) & LPI2C_MCR_RTF_MASK)
+#define LPI2C_MCR_RRF_MASK (0x200U)
+#define LPI2C_MCR_RRF_SHIFT (9U)
+#define LPI2C_MCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RRF_SHIFT)) & LPI2C_MCR_RRF_MASK)
+
+/*! @name MSR - Master Status Register */
+#define LPI2C_MSR_TDF_MASK (0x1U)
+#define LPI2C_MSR_TDF_SHIFT (0U)
+#define LPI2C_MSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_TDF_SHIFT)) & LPI2C_MSR_TDF_MASK)
+#define LPI2C_MSR_RDF_MASK (0x2U)
+#define LPI2C_MSR_RDF_SHIFT (1U)
+#define LPI2C_MSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_RDF_SHIFT)) & LPI2C_MSR_RDF_MASK)
+#define LPI2C_MSR_EPF_MASK (0x100U)
+#define LPI2C_MSR_EPF_SHIFT (8U)
+#define LPI2C_MSR_EPF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_EPF_SHIFT)) & LPI2C_MSR_EPF_MASK)
+#define LPI2C_MSR_SDF_MASK (0x200U)
+#define LPI2C_MSR_SDF_SHIFT (9U)
+#define LPI2C_MSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_SDF_SHIFT)) & LPI2C_MSR_SDF_MASK)
+#define LPI2C_MSR_NDF_MASK (0x400U)
+#define LPI2C_MSR_NDF_SHIFT (10U)
+#define LPI2C_MSR_NDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_NDF_SHIFT)) & LPI2C_MSR_NDF_MASK)
+#define LPI2C_MSR_ALF_MASK (0x800U)
+#define LPI2C_MSR_ALF_SHIFT (11U)
+#define LPI2C_MSR_ALF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_ALF_SHIFT)) & LPI2C_MSR_ALF_MASK)
+#define LPI2C_MSR_FEF_MASK (0x1000U)
+#define LPI2C_MSR_FEF_SHIFT (12U)
+#define LPI2C_MSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_FEF_SHIFT)) & LPI2C_MSR_FEF_MASK)
+#define LPI2C_MSR_PLTF_MASK (0x2000U)
+#define LPI2C_MSR_PLTF_SHIFT (13U)
+#define LPI2C_MSR_PLTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_PLTF_SHIFT)) & LPI2C_MSR_PLTF_MASK)
+#define LPI2C_MSR_DMF_MASK (0x4000U)
+#define LPI2C_MSR_DMF_SHIFT (14U)
+#define LPI2C_MSR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_DMF_SHIFT)) & LPI2C_MSR_DMF_MASK)
+#define LPI2C_MSR_MBF_MASK (0x1000000U)
+#define LPI2C_MSR_MBF_SHIFT (24U)
+#define LPI2C_MSR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_MBF_SHIFT)) & LPI2C_MSR_MBF_MASK)
+#define LPI2C_MSR_BBF_MASK (0x2000000U)
+#define LPI2C_MSR_BBF_SHIFT (25U)
+#define LPI2C_MSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_BBF_SHIFT)) & LPI2C_MSR_BBF_MASK)
+
+/*! @name MIER - Master Interrupt Enable Register */
+#define LPI2C_MIER_TDIE_MASK (0x1U)
+#define LPI2C_MIER_TDIE_SHIFT (0U)
+#define LPI2C_MIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_TDIE_SHIFT)) & LPI2C_MIER_TDIE_MASK)
+#define LPI2C_MIER_RDIE_MASK (0x2U)
+#define LPI2C_MIER_RDIE_SHIFT (1U)
+#define LPI2C_MIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_RDIE_SHIFT)) & LPI2C_MIER_RDIE_MASK)
+#define LPI2C_MIER_EPIE_MASK (0x100U)
+#define LPI2C_MIER_EPIE_SHIFT (8U)
+#define LPI2C_MIER_EPIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_EPIE_SHIFT)) & LPI2C_MIER_EPIE_MASK)
+#define LPI2C_MIER_SDIE_MASK (0x200U)
+#define LPI2C_MIER_SDIE_SHIFT (9U)
+#define LPI2C_MIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_SDIE_SHIFT)) & LPI2C_MIER_SDIE_MASK)
+#define LPI2C_MIER_NDIE_MASK (0x400U)
+#define LPI2C_MIER_NDIE_SHIFT (10U)
+#define LPI2C_MIER_NDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_NDIE_SHIFT)) & LPI2C_MIER_NDIE_MASK)
+#define LPI2C_MIER_ALIE_MASK (0x800U)
+#define LPI2C_MIER_ALIE_SHIFT (11U)
+#define LPI2C_MIER_ALIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_ALIE_SHIFT)) & LPI2C_MIER_ALIE_MASK)
+#define LPI2C_MIER_FEIE_MASK (0x1000U)
+#define LPI2C_MIER_FEIE_SHIFT (12U)
+#define LPI2C_MIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_FEIE_SHIFT)) & LPI2C_MIER_FEIE_MASK)
+#define LPI2C_MIER_PLTIE_MASK (0x2000U)
+#define LPI2C_MIER_PLTIE_SHIFT (13U)
+#define LPI2C_MIER_PLTIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_PLTIE_SHIFT)) & LPI2C_MIER_PLTIE_MASK)
+#define LPI2C_MIER_DMIE_MASK (0x4000U)
+#define LPI2C_MIER_DMIE_SHIFT (14U)
+#define LPI2C_MIER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_DMIE_SHIFT)) & LPI2C_MIER_DMIE_MASK)
+
+/*! @name MDER - Master DMA Enable Register */
+#define LPI2C_MDER_TDDE_MASK (0x1U)
+#define LPI2C_MDER_TDDE_SHIFT (0U)
+#define LPI2C_MDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_TDDE_SHIFT)) & LPI2C_MDER_TDDE_MASK)
+#define LPI2C_MDER_RDDE_MASK (0x2U)
+#define LPI2C_MDER_RDDE_SHIFT (1U)
+#define LPI2C_MDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_RDDE_SHIFT)) & LPI2C_MDER_RDDE_MASK)
+
+/*! @name MCFGR0 - Master Configuration Register 0 */
+#define LPI2C_MCFGR0_HREN_MASK (0x1U)
+#define LPI2C_MCFGR0_HREN_SHIFT (0U)
+#define LPI2C_MCFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HREN_SHIFT)) & LPI2C_MCFGR0_HREN_MASK)
+#define LPI2C_MCFGR0_HRPOL_MASK (0x2U)
+#define LPI2C_MCFGR0_HRPOL_SHIFT (1U)
+#define LPI2C_MCFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRPOL_SHIFT)) & LPI2C_MCFGR0_HRPOL_MASK)
+#define LPI2C_MCFGR0_HRSEL_MASK (0x4U)
+#define LPI2C_MCFGR0_HRSEL_SHIFT (2U)
+#define LPI2C_MCFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRSEL_SHIFT)) & LPI2C_MCFGR0_HRSEL_MASK)
+#define LPI2C_MCFGR0_CIRFIFO_MASK (0x100U)
+#define LPI2C_MCFGR0_CIRFIFO_SHIFT (8U)
+#define LPI2C_MCFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_CIRFIFO_SHIFT)) & LPI2C_MCFGR0_CIRFIFO_MASK)
+#define LPI2C_MCFGR0_RDMO_MASK (0x200U)
+#define LPI2C_MCFGR0_RDMO_SHIFT (9U)
+#define LPI2C_MCFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_RDMO_SHIFT)) & LPI2C_MCFGR0_RDMO_MASK)
+
+/*! @name MCFGR1 - Master Configuration Register 1 */
+#define LPI2C_MCFGR1_PRESCALE_MASK (0x7U)
+#define LPI2C_MCFGR1_PRESCALE_SHIFT (0U)
+#define LPI2C_MCFGR1_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PRESCALE_SHIFT)) & LPI2C_MCFGR1_PRESCALE_MASK)
+#define LPI2C_MCFGR1_AUTOSTOP_MASK (0x100U)
+#define LPI2C_MCFGR1_AUTOSTOP_SHIFT (8U)
+#define LPI2C_MCFGR1_AUTOSTOP(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_AUTOSTOP_SHIFT)) & LPI2C_MCFGR1_AUTOSTOP_MASK)
+#define LPI2C_MCFGR1_IGNACK_MASK (0x200U)
+#define LPI2C_MCFGR1_IGNACK_SHIFT (9U)
+#define LPI2C_MCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_IGNACK_SHIFT)) & LPI2C_MCFGR1_IGNACK_MASK)
+#define LPI2C_MCFGR1_TIMECFG_MASK (0x400U)
+#define LPI2C_MCFGR1_TIMECFG_SHIFT (10U)
+#define LPI2C_MCFGR1_TIMECFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_TIMECFG_SHIFT)) & LPI2C_MCFGR1_TIMECFG_MASK)
+#define LPI2C_MCFGR1_MATCFG_MASK (0x70000U)
+#define LPI2C_MCFGR1_MATCFG_SHIFT (16U)
+#define LPI2C_MCFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_MATCFG_SHIFT)) & LPI2C_MCFGR1_MATCFG_MASK)
+#define LPI2C_MCFGR1_PINCFG_MASK (0x7000000U)
+#define LPI2C_MCFGR1_PINCFG_SHIFT (24U)
+#define LPI2C_MCFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PINCFG_SHIFT)) & LPI2C_MCFGR1_PINCFG_MASK)
+
+/*! @name MCFGR2 - Master Configuration Register 2 */
+#define LPI2C_MCFGR2_BUSIDLE_MASK (0xFFFU)
+#define LPI2C_MCFGR2_BUSIDLE_SHIFT (0U)
+#define LPI2C_MCFGR2_BUSIDLE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_BUSIDLE_SHIFT)) & LPI2C_MCFGR2_BUSIDLE_MASK)
+#define LPI2C_MCFGR2_FILTSCL_MASK (0xF0000U)
+#define LPI2C_MCFGR2_FILTSCL_SHIFT (16U)
+#define LPI2C_MCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSCL_SHIFT)) & LPI2C_MCFGR2_FILTSCL_MASK)
+#define LPI2C_MCFGR2_FILTSDA_MASK (0xF000000U)
+#define LPI2C_MCFGR2_FILTSDA_SHIFT (24U)
+#define LPI2C_MCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSDA_SHIFT)) & LPI2C_MCFGR2_FILTSDA_MASK)
+
+/*! @name MCFGR3 - Master Configuration Register 3 */
+#define LPI2C_MCFGR3_PINLOW_MASK (0xFFF00U)
+#define LPI2C_MCFGR3_PINLOW_SHIFT (8U)
+#define LPI2C_MCFGR3_PINLOW(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR3_PINLOW_SHIFT)) & LPI2C_MCFGR3_PINLOW_MASK)
+
+/*! @name MDMR - Master Data Match Register */
+#define LPI2C_MDMR_MATCH0_MASK (0xFFU)
+#define LPI2C_MDMR_MATCH0_SHIFT (0U)
+#define LPI2C_MDMR_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH0_SHIFT)) & LPI2C_MDMR_MATCH0_MASK)
+#define LPI2C_MDMR_MATCH1_MASK (0xFF0000U)
+#define LPI2C_MDMR_MATCH1_SHIFT (16U)
+#define LPI2C_MDMR_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH1_SHIFT)) & LPI2C_MDMR_MATCH1_MASK)
+
+/*! @name MCCR0 - Master Clock Configuration Register 0 */
+#define LPI2C_MCCR0_CLKLO_MASK (0x3FU)
+#define LPI2C_MCCR0_CLKLO_SHIFT (0U)
+#define LPI2C_MCCR0_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKLO_SHIFT)) & LPI2C_MCCR0_CLKLO_MASK)
+#define LPI2C_MCCR0_CLKHI_MASK (0x3F00U)
+#define LPI2C_MCCR0_CLKHI_SHIFT (8U)
+#define LPI2C_MCCR0_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKHI_SHIFT)) & LPI2C_MCCR0_CLKHI_MASK)
+#define LPI2C_MCCR0_SETHOLD_MASK (0x3F0000U)
+#define LPI2C_MCCR0_SETHOLD_SHIFT (16U)
+#define LPI2C_MCCR0_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_SETHOLD_SHIFT)) & LPI2C_MCCR0_SETHOLD_MASK)
+#define LPI2C_MCCR0_DATAVD_MASK (0x3F000000U)
+#define LPI2C_MCCR0_DATAVD_SHIFT (24U)
+#define LPI2C_MCCR0_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_DATAVD_SHIFT)) & LPI2C_MCCR0_DATAVD_MASK)
+
+/*! @name MCCR1 - Master Clock Configuration Register 1 */
+#define LPI2C_MCCR1_CLKLO_MASK (0x3FU)
+#define LPI2C_MCCR1_CLKLO_SHIFT (0U)
+#define LPI2C_MCCR1_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKLO_SHIFT)) & LPI2C_MCCR1_CLKLO_MASK)
+#define LPI2C_MCCR1_CLKHI_MASK (0x3F00U)
+#define LPI2C_MCCR1_CLKHI_SHIFT (8U)
+#define LPI2C_MCCR1_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKHI_SHIFT)) & LPI2C_MCCR1_CLKHI_MASK)
+#define LPI2C_MCCR1_SETHOLD_MASK (0x3F0000U)
+#define LPI2C_MCCR1_SETHOLD_SHIFT (16U)
+#define LPI2C_MCCR1_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_SETHOLD_SHIFT)) & LPI2C_MCCR1_SETHOLD_MASK)
+#define LPI2C_MCCR1_DATAVD_MASK (0x3F000000U)
+#define LPI2C_MCCR1_DATAVD_SHIFT (24U)
+#define LPI2C_MCCR1_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_DATAVD_SHIFT)) & LPI2C_MCCR1_DATAVD_MASK)
+
+/*! @name MFCR - Master FIFO Control Register */
+#define LPI2C_MFCR_TXWATER_MASK (0xFFU)
+#define LPI2C_MFCR_TXWATER_SHIFT (0U)
+#define LPI2C_MFCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_TXWATER_SHIFT)) & LPI2C_MFCR_TXWATER_MASK)
+#define LPI2C_MFCR_RXWATER_MASK (0xFF0000U)
+#define LPI2C_MFCR_RXWATER_SHIFT (16U)
+#define LPI2C_MFCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_RXWATER_SHIFT)) & LPI2C_MFCR_RXWATER_MASK)
+
+/*! @name MFSR - Master FIFO Status Register */
+#define LPI2C_MFSR_TXCOUNT_MASK (0xFFU)
+#define LPI2C_MFSR_TXCOUNT_SHIFT (0U)
+#define LPI2C_MFSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_TXCOUNT_SHIFT)) & LPI2C_MFSR_TXCOUNT_MASK)
+#define LPI2C_MFSR_RXCOUNT_MASK (0xFF0000U)
+#define LPI2C_MFSR_RXCOUNT_SHIFT (16U)
+#define LPI2C_MFSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_RXCOUNT_SHIFT)) & LPI2C_MFSR_RXCOUNT_MASK)
+
+/*! @name MTDR - Master Transmit Data Register */
+#define LPI2C_MTDR_DATA_MASK (0xFFU)
+#define LPI2C_MTDR_DATA_SHIFT (0U)
+#define LPI2C_MTDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_DATA_SHIFT)) & LPI2C_MTDR_DATA_MASK)
+#define LPI2C_MTDR_CMD_MASK (0x700U)
+#define LPI2C_MTDR_CMD_SHIFT (8U)
+#define LPI2C_MTDR_CMD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_CMD_SHIFT)) & LPI2C_MTDR_CMD_MASK)
+
+/*! @name MRDR - Master Receive Data Register */
+#define LPI2C_MRDR_DATA_MASK (0xFFU)
+#define LPI2C_MRDR_DATA_SHIFT (0U)
+#define LPI2C_MRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_DATA_SHIFT)) & LPI2C_MRDR_DATA_MASK)
+#define LPI2C_MRDR_RXEMPTY_MASK (0x4000U)
+#define LPI2C_MRDR_RXEMPTY_SHIFT (14U)
+#define LPI2C_MRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_RXEMPTY_SHIFT)) & LPI2C_MRDR_RXEMPTY_MASK)
+
+/*! @name SCR - Slave Control Register */
+#define LPI2C_SCR_SEN_MASK (0x1U)
+#define LPI2C_SCR_SEN_SHIFT (0U)
+#define LPI2C_SCR_SEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_SEN_SHIFT)) & LPI2C_SCR_SEN_MASK)
+#define LPI2C_SCR_RST_MASK (0x2U)
+#define LPI2C_SCR_RST_SHIFT (1U)
+#define LPI2C_SCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RST_SHIFT)) & LPI2C_SCR_RST_MASK)
+#define LPI2C_SCR_FILTEN_MASK (0x10U)
+#define LPI2C_SCR_FILTEN_SHIFT (4U)
+#define LPI2C_SCR_FILTEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTEN_SHIFT)) & LPI2C_SCR_FILTEN_MASK)
+#define LPI2C_SCR_FILTDZ_MASK (0x20U)
+#define LPI2C_SCR_FILTDZ_SHIFT (5U)
+#define LPI2C_SCR_FILTDZ(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTDZ_SHIFT)) & LPI2C_SCR_FILTDZ_MASK)
+#define LPI2C_SCR_RTF_MASK (0x100U)
+#define LPI2C_SCR_RTF_SHIFT (8U)
+#define LPI2C_SCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RTF_SHIFT)) & LPI2C_SCR_RTF_MASK)
+#define LPI2C_SCR_RRF_MASK (0x200U)
+#define LPI2C_SCR_RRF_SHIFT (9U)
+#define LPI2C_SCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RRF_SHIFT)) & LPI2C_SCR_RRF_MASK)
+
+/*! @name SSR - Slave Status Register */
+#define LPI2C_SSR_TDF_MASK (0x1U)
+#define LPI2C_SSR_TDF_SHIFT (0U)
+#define LPI2C_SSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TDF_SHIFT)) & LPI2C_SSR_TDF_MASK)
+#define LPI2C_SSR_RDF_MASK (0x2U)
+#define LPI2C_SSR_RDF_SHIFT (1U)
+#define LPI2C_SSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RDF_SHIFT)) & LPI2C_SSR_RDF_MASK)
+#define LPI2C_SSR_AVF_MASK (0x4U)
+#define LPI2C_SSR_AVF_SHIFT (2U)
+#define LPI2C_SSR_AVF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AVF_SHIFT)) & LPI2C_SSR_AVF_MASK)
+#define LPI2C_SSR_TAF_MASK (0x8U)
+#define LPI2C_SSR_TAF_SHIFT (3U)
+#define LPI2C_SSR_TAF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TAF_SHIFT)) & LPI2C_SSR_TAF_MASK)
+#define LPI2C_SSR_RSF_MASK (0x100U)
+#define LPI2C_SSR_RSF_SHIFT (8U)
+#define LPI2C_SSR_RSF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RSF_SHIFT)) & LPI2C_SSR_RSF_MASK)
+#define LPI2C_SSR_SDF_MASK (0x200U)
+#define LPI2C_SSR_SDF_SHIFT (9U)
+#define LPI2C_SSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SDF_SHIFT)) & LPI2C_SSR_SDF_MASK)
+#define LPI2C_SSR_BEF_MASK (0x400U)
+#define LPI2C_SSR_BEF_SHIFT (10U)
+#define LPI2C_SSR_BEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BEF_SHIFT)) & LPI2C_SSR_BEF_MASK)
+#define LPI2C_SSR_FEF_MASK (0x800U)
+#define LPI2C_SSR_FEF_SHIFT (11U)
+#define LPI2C_SSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_FEF_SHIFT)) & LPI2C_SSR_FEF_MASK)
+#define LPI2C_SSR_AM0F_MASK (0x1000U)
+#define LPI2C_SSR_AM0F_SHIFT (12U)
+#define LPI2C_SSR_AM0F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM0F_SHIFT)) & LPI2C_SSR_AM0F_MASK)
+#define LPI2C_SSR_AM1F_MASK (0x2000U)
+#define LPI2C_SSR_AM1F_SHIFT (13U)
+#define LPI2C_SSR_AM1F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM1F_SHIFT)) & LPI2C_SSR_AM1F_MASK)
+#define LPI2C_SSR_GCF_MASK (0x4000U)
+#define LPI2C_SSR_GCF_SHIFT (14U)
+#define LPI2C_SSR_GCF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_GCF_SHIFT)) & LPI2C_SSR_GCF_MASK)
+#define LPI2C_SSR_SARF_MASK (0x8000U)
+#define LPI2C_SSR_SARF_SHIFT (15U)
+#define LPI2C_SSR_SARF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SARF_SHIFT)) & LPI2C_SSR_SARF_MASK)
+#define LPI2C_SSR_SBF_MASK (0x1000000U)
+#define LPI2C_SSR_SBF_SHIFT (24U)
+#define LPI2C_SSR_SBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SBF_SHIFT)) & LPI2C_SSR_SBF_MASK)
+#define LPI2C_SSR_BBF_MASK (0x2000000U)
+#define LPI2C_SSR_BBF_SHIFT (25U)
+#define LPI2C_SSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BBF_SHIFT)) & LPI2C_SSR_BBF_MASK)
+
+/*! @name SIER - Slave Interrupt Enable Register */
+#define LPI2C_SIER_TDIE_MASK (0x1U)
+#define LPI2C_SIER_TDIE_SHIFT (0U)
+#define LPI2C_SIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TDIE_SHIFT)) & LPI2C_SIER_TDIE_MASK)
+#define LPI2C_SIER_RDIE_MASK (0x2U)
+#define LPI2C_SIER_RDIE_SHIFT (1U)
+#define LPI2C_SIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RDIE_SHIFT)) & LPI2C_SIER_RDIE_MASK)
+#define LPI2C_SIER_AVIE_MASK (0x4U)
+#define LPI2C_SIER_AVIE_SHIFT (2U)
+#define LPI2C_SIER_AVIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AVIE_SHIFT)) & LPI2C_SIER_AVIE_MASK)
+#define LPI2C_SIER_TAIE_MASK (0x8U)
+#define LPI2C_SIER_TAIE_SHIFT (3U)
+#define LPI2C_SIER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TAIE_SHIFT)) & LPI2C_SIER_TAIE_MASK)
+#define LPI2C_SIER_RSIE_MASK (0x100U)
+#define LPI2C_SIER_RSIE_SHIFT (8U)
+#define LPI2C_SIER_RSIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RSIE_SHIFT)) & LPI2C_SIER_RSIE_MASK)
+#define LPI2C_SIER_SDIE_MASK (0x200U)
+#define LPI2C_SIER_SDIE_SHIFT (9U)
+#define LPI2C_SIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SDIE_SHIFT)) & LPI2C_SIER_SDIE_MASK)
+#define LPI2C_SIER_BEIE_MASK (0x400U)
+#define LPI2C_SIER_BEIE_SHIFT (10U)
+#define LPI2C_SIER_BEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_BEIE_SHIFT)) & LPI2C_SIER_BEIE_MASK)
+#define LPI2C_SIER_FEIE_MASK (0x800U)
+#define LPI2C_SIER_FEIE_SHIFT (11U)
+#define LPI2C_SIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_FEIE_SHIFT)) & LPI2C_SIER_FEIE_MASK)
+#define LPI2C_SIER_AM0IE_MASK (0x1000U)
+#define LPI2C_SIER_AM0IE_SHIFT (12U)
+#define LPI2C_SIER_AM0IE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM0IE_SHIFT)) & LPI2C_SIER_AM0IE_MASK)
+#define LPI2C_SIER_AM1F_MASK (0x2000U)
+#define LPI2C_SIER_AM1F_SHIFT (13U)
+#define LPI2C_SIER_AM1F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM1F_SHIFT)) & LPI2C_SIER_AM1F_MASK)
+#define LPI2C_SIER_GCIE_MASK (0x4000U)
+#define LPI2C_SIER_GCIE_SHIFT (14U)
+#define LPI2C_SIER_GCIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_GCIE_SHIFT)) & LPI2C_SIER_GCIE_MASK)
+#define LPI2C_SIER_SARIE_MASK (0x8000U)
+#define LPI2C_SIER_SARIE_SHIFT (15U)
+#define LPI2C_SIER_SARIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SARIE_SHIFT)) & LPI2C_SIER_SARIE_MASK)
+
+/*! @name SDER - Slave DMA Enable Register */
+#define LPI2C_SDER_TDDE_MASK (0x1U)
+#define LPI2C_SDER_TDDE_SHIFT (0U)
+#define LPI2C_SDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_TDDE_SHIFT)) & LPI2C_SDER_TDDE_MASK)
+#define LPI2C_SDER_RDDE_MASK (0x2U)
+#define LPI2C_SDER_RDDE_SHIFT (1U)
+#define LPI2C_SDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RDDE_SHIFT)) & LPI2C_SDER_RDDE_MASK)
+#define LPI2C_SDER_AVDE_MASK (0x4U)
+#define LPI2C_SDER_AVDE_SHIFT (2U)
+#define LPI2C_SDER_AVDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_AVDE_SHIFT)) & LPI2C_SDER_AVDE_MASK)
+
+/*! @name SCFGR1 - Slave Configuration Register 1 */
+#define LPI2C_SCFGR1_ADRSTALL_MASK (0x1U)
+#define LPI2C_SCFGR1_ADRSTALL_SHIFT (0U)
+#define LPI2C_SCFGR1_ADRSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADRSTALL_SHIFT)) & LPI2C_SCFGR1_ADRSTALL_MASK)
+#define LPI2C_SCFGR1_RXSTALL_MASK (0x2U)
+#define LPI2C_SCFGR1_RXSTALL_SHIFT (1U)
+#define LPI2C_SCFGR1_RXSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXSTALL_SHIFT)) & LPI2C_SCFGR1_RXSTALL_MASK)
+#define LPI2C_SCFGR1_TXDSTALL_MASK (0x4U)
+#define LPI2C_SCFGR1_TXDSTALL_SHIFT (2U)
+#define LPI2C_SCFGR1_TXDSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXDSTALL_SHIFT)) & LPI2C_SCFGR1_TXDSTALL_MASK)
+#define LPI2C_SCFGR1_ACKSTALL_MASK (0x8U)
+#define LPI2C_SCFGR1_ACKSTALL_SHIFT (3U)
+#define LPI2C_SCFGR1_ACKSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ACKSTALL_SHIFT)) & LPI2C_SCFGR1_ACKSTALL_MASK)
+#define LPI2C_SCFGR1_GCEN_MASK (0x100U)
+#define LPI2C_SCFGR1_GCEN_SHIFT (8U)
+#define LPI2C_SCFGR1_GCEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_GCEN_SHIFT)) & LPI2C_SCFGR1_GCEN_MASK)
+#define LPI2C_SCFGR1_SAEN_MASK (0x200U)
+#define LPI2C_SCFGR1_SAEN_SHIFT (9U)
+#define LPI2C_SCFGR1_SAEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_SAEN_SHIFT)) & LPI2C_SCFGR1_SAEN_MASK)
+#define LPI2C_SCFGR1_TXCFG_MASK (0x400U)
+#define LPI2C_SCFGR1_TXCFG_SHIFT (10U)
+#define LPI2C_SCFGR1_TXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXCFG_SHIFT)) & LPI2C_SCFGR1_TXCFG_MASK)
+#define LPI2C_SCFGR1_RXCFG_MASK (0x800U)
+#define LPI2C_SCFGR1_RXCFG_SHIFT (11U)
+#define LPI2C_SCFGR1_RXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXCFG_SHIFT)) & LPI2C_SCFGR1_RXCFG_MASK)
+#define LPI2C_SCFGR1_IGNACK_MASK (0x1000U)
+#define LPI2C_SCFGR1_IGNACK_SHIFT (12U)
+#define LPI2C_SCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_IGNACK_SHIFT)) & LPI2C_SCFGR1_IGNACK_MASK)
+#define LPI2C_SCFGR1_HSMEN_MASK (0x2000U)
+#define LPI2C_SCFGR1_HSMEN_SHIFT (13U)
+#define LPI2C_SCFGR1_HSMEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_HSMEN_SHIFT)) & LPI2C_SCFGR1_HSMEN_MASK)
+#define LPI2C_SCFGR1_ADDRCFG_MASK (0x70000U)
+#define LPI2C_SCFGR1_ADDRCFG_SHIFT (16U)
+#define LPI2C_SCFGR1_ADDRCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADDRCFG_SHIFT)) & LPI2C_SCFGR1_ADDRCFG_MASK)
+
+/*! @name SCFGR2 - Slave Configuration Register 2 */
+#define LPI2C_SCFGR2_CLKHOLD_MASK (0xFU)
+#define LPI2C_SCFGR2_CLKHOLD_SHIFT (0U)
+#define LPI2C_SCFGR2_CLKHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_CLKHOLD_SHIFT)) & LPI2C_SCFGR2_CLKHOLD_MASK)
+#define LPI2C_SCFGR2_DATAVD_MASK (0x3F00U)
+#define LPI2C_SCFGR2_DATAVD_SHIFT (8U)
+#define LPI2C_SCFGR2_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_DATAVD_SHIFT)) & LPI2C_SCFGR2_DATAVD_MASK)
+#define LPI2C_SCFGR2_FILTSCL_MASK (0xF0000U)
+#define LPI2C_SCFGR2_FILTSCL_SHIFT (16U)
+#define LPI2C_SCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSCL_SHIFT)) & LPI2C_SCFGR2_FILTSCL_MASK)
+#define LPI2C_SCFGR2_FILTSDA_MASK (0xF000000U)
+#define LPI2C_SCFGR2_FILTSDA_SHIFT (24U)
+#define LPI2C_SCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSDA_SHIFT)) & LPI2C_SCFGR2_FILTSDA_MASK)
+
+/*! @name SAMR - Slave Address Match Register */
+#define LPI2C_SAMR_ADDR0_MASK (0x7FEU)
+#define LPI2C_SAMR_ADDR0_SHIFT (1U)
+#define LPI2C_SAMR_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR0_SHIFT)) & LPI2C_SAMR_ADDR0_MASK)
+#define LPI2C_SAMR_ADDR1_MASK (0x7FE0000U)
+#define LPI2C_SAMR_ADDR1_SHIFT (17U)
+#define LPI2C_SAMR_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR1_SHIFT)) & LPI2C_SAMR_ADDR1_MASK)
+
+/*! @name SASR - Slave Address Status Register */
+#define LPI2C_SASR_RADDR_MASK (0x7FFU)
+#define LPI2C_SASR_RADDR_SHIFT (0U)
+#define LPI2C_SASR_RADDR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_RADDR_SHIFT)) & LPI2C_SASR_RADDR_MASK)
+#define LPI2C_SASR_ANV_MASK (0x4000U)
+#define LPI2C_SASR_ANV_SHIFT (14U)
+#define LPI2C_SASR_ANV(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_ANV_SHIFT)) & LPI2C_SASR_ANV_MASK)
+
+/*! @name STAR - Slave Transmit ACK Register */
+#define LPI2C_STAR_TXNACK_MASK (0x1U)
+#define LPI2C_STAR_TXNACK_SHIFT (0U)
+#define LPI2C_STAR_TXNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STAR_TXNACK_SHIFT)) & LPI2C_STAR_TXNACK_MASK)
+
+/*! @name STDR - Slave Transmit Data Register */
+#define LPI2C_STDR_DATA_MASK (0xFFU)
+#define LPI2C_STDR_DATA_SHIFT (0U)
+#define LPI2C_STDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STDR_DATA_SHIFT)) & LPI2C_STDR_DATA_MASK)
+
+/*! @name SRDR - Slave Receive Data Register */
+#define LPI2C_SRDR_DATA_MASK (0xFFU)
+#define LPI2C_SRDR_DATA_SHIFT (0U)
+#define LPI2C_SRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_DATA_SHIFT)) & LPI2C_SRDR_DATA_MASK)
+#define LPI2C_SRDR_RXEMPTY_MASK (0x4000U)
+#define LPI2C_SRDR_RXEMPTY_SHIFT (14U)
+#define LPI2C_SRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RXEMPTY_SHIFT)) & LPI2C_SRDR_RXEMPTY_MASK)
+#define LPI2C_SRDR_SOF_MASK (0x8000U)
+#define LPI2C_SRDR_SOF_SHIFT (15U)
+#define LPI2C_SRDR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_SOF_SHIFT)) & LPI2C_SRDR_SOF_MASK)
+
+#endif /* __ASM_ARCH_IMX_I2C_H__ */
diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
index 39f62da..8ac7aaf 100644
--- a/drivers/i2c/Kconfig
+++ b/drivers/i2c/Kconfig
@@ -109,6 +109,12 @@ config SYS_I2C_INTEL
the I2C API meaning that any I2C operations will immediately fail
for now.
+config SYS_I2C_IMX_LPI2C
+ bool "NXP i.MX LPI2C driver"
+ depends on ARCH_MX7ULP
+ help
+ Add support for the NXP i.MX LPI2C driver.
+
config SYS_I2C_MXC
bool "NXP i.MX I2C driver"
depends on MX6
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index 7c86198..446af22 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -24,6 +24,7 @@ obj-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o
obj-$(CONFIG_SYS_I2C_FTI2C010) += fti2c010.o
obj-$(CONFIG_SYS_I2C_IHS) += ihs_i2c.o
obj-$(CONFIG_SYS_I2C_INTEL) += intel_i2c.o
+obj-$(CONFIG_SYS_I2C_IMX_LPI2C) += imx_lpi2c.o
obj-$(CONFIG_SYS_I2C_KONA) += kona_i2c.o
obj-$(CONFIG_SYS_I2C_LPC32XX) += lpc32xx_i2c.o
obj-$(CONFIG_SYS_I2C_MVTWSI) += mvtwsi.o
diff --git a/drivers/i2c/imx_lpi2c.c b/drivers/i2c/imx_lpi2c.c
new file mode 100644
index 0000000..f792d44
--- /dev/null
+++ b/drivers/i2c/imx_lpi2c.c
@@ -0,0 +1,462 @@
+/*
+ * Copyright 2016 Freescale Semiconductors, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/imx_lpi2c.h>
+#include <asm/arch/sys_proto.h>
+#include <dm.h>
+#include <fdtdec.h>
+#include <i2c.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+#define LPI2C_FIFO_SIZE 4
+#define LPI2C_TIMEOUT_MS 100
+
+/* Weak linked function for overridden by some SoC power function */
+int __weak init_i2c_power(unsigned i2c_num)
+{
+ return 0;
+}
+
+static int imx_lpci2c_check_busy_bus(struct udevice *bus)
+{
+ struct imx_lpi2c_reg *regs = (struct imx_lpi2c_reg *)dev_get_addr(bus);
+ lpi2c_status_t result = LPI2C_SUCESS;
+ u32 status;
+
+ status = readl(®s->msr);
+
+ if ((status & LPI2C_MSR_BBF_MASK) && !(status & LPI2C_MSR_MBF_MASK))
+ result = LPI2C_BUSY;
+
+ return result;
+}
+
+static int imx_lpci2c_check_clear_error(struct udevice *bus)
+{
+ struct imx_lpi2c_reg *regs = (struct imx_lpi2c_reg *)dev_get_addr(bus);
+ lpi2c_status_t result = LPI2C_SUCESS;
+ u32 val, status;
+
+ status = readl(®s->msr);
+ /* errors to check for */
+ status &= LPI2C_MSR_NDF_MASK | LPI2C_MSR_ALF_MASK |
+ LPI2C_MSR_FEF_MASK | LPI2C_MSR_PLTF_MASK;
+
+ if (status) {
+ if (status & LPI2C_MSR_PLTF_MASK)
+ result = LPI2C_PIN_LOW_TIMEOUT_ERR;
+ else if (status & LPI2C_MSR_ALF_MASK)
+ result = LPI2C_ARB_LOST_ERR;
+ else if (status & LPI2C_MSR_NDF_MASK)
+ result = LPI2C_NAK_ERR;
+ else if (status & LPI2C_MSR_FEF_MASK)
+ result = LPI2C_FIFO_ERR;
+
+ /* clear status flags */
+ writel(0x7f00, ®s->msr);
+ /* reset fifos */
+ val = readl(®s->mcr);
+ val |= LPI2C_MCR_RRF_MASK | LPI2C_MCR_RTF_MASK;
+ writel(val, ®s->mcr);
+ }
+
+ return result;
+}
+
+static int bus_i2c_wait_for_tx_ready(struct udevice *bus)
+{
+ struct imx_lpi2c_reg *regs = (struct imx_lpi2c_reg *)dev_get_addr(bus);
+ lpi2c_status_t result = LPI2C_SUCESS;
+ u32 txcount = 0;
+ ulong start_time = get_timer(0);
+
+ do {
+ txcount = LPI2C_MFSR_TXCOUNT(readl(®s->mfsr));
+ txcount = LPI2C_FIFO_SIZE - txcount;
+ result = imx_lpci2c_check_clear_error(bus);
+ if (result) {
+ debug("i2c: wait for tx ready: result 0x%x\n", result);
+ return result;
+ }
+ if (get_timer(start_time) > LPI2C_TIMEOUT_MS) {
+ debug("i2c: wait for tx ready: timeout\n");
+ return -1;
+ }
+ } while (!txcount);
+
+ return result;
+}
+
+static int bus_i2c_send(struct udevice *bus, u8 *txbuf, int len)
+{
+ struct imx_lpi2c_reg *regs = (struct imx_lpi2c_reg *)dev_get_addr(bus);
+ lpi2c_status_t result = LPI2C_SUCESS;
+
+ /* empty tx */
+ if (!len)
+ return result;
+
+ while (len--) {
+ result = bus_i2c_wait_for_tx_ready(bus);
+ if (result) {
+ debug("i2c: send wait fot tx ready: %d\n", result);
+ return result;
+ }
+ writel(*txbuf++, ®s->mtdr);
+ }
+
+ return result;
+}
+
+static int bus_i2c_receive(struct udevice *bus, u8 *rxbuf, int len)
+{
+ struct imx_lpi2c_reg *regs = (struct imx_lpi2c_reg *)dev_get_addr(bus);
+ lpi2c_status_t result = LPI2C_SUCESS;
+ u32 val;
+ ulong start_time = get_timer(0);
+
+ /* empty read */
+ if (!len)
+ return result;
+
+ result = bus_i2c_wait_for_tx_ready(bus);
+ if (result) {
+ debug("i2c: receive wait fot tx ready: %d\n", result);
+ return result;
+ }
+
+ /* clear all status flags */
+ writel(0x7f00, ®s->msr);
+ /* send receive command */
+ val = LPI2C_MTDR_CMD(0x1) | LPI2C_MTDR_DATA(len - 1);
+ writel(val, ®s->mtdr);
+
+ while (len--) {
+ do {
+ result = imx_lpci2c_check_clear_error(bus);
+ if (result) {
+ debug("i2c: receive check clear error: %d\n", result);
+ return result;
+ }
+ if (get_timer(start_time) > LPI2C_TIMEOUT_MS) {
+ debug("i2c: receive mrdr: timeout\n");
+ return -1;
+ }
+ val = readl(®s->mrdr);
+ } while (val & LPI2C_MRDR_RXEMPTY_MASK);
+ *rxbuf++ = LPI2C_MRDR_DATA(val);
+ }
+
+ return result;
+}
+
+static int bus_i2c_start(struct udevice *bus, u8 addr, u8 dir)
+{
+ struct imx_lpi2c_reg *regs = (struct imx_lpi2c_reg *)dev_get_addr(bus);
+ lpi2c_status_t result = LPI2C_SUCESS;
+ u32 val;
+
+ result = imx_lpci2c_check_busy_bus(bus);
+ if (result) {
+ debug("i2c: start check busy bus: 0x%x\n", result);
+ return result;
+ }
+ /* clear all status flags */
+ writel(0x7f00, ®s->msr);
+ /* turn off auto-stop condition */
+ val = readl(®s->mcfgr1) & ~LPI2C_MCFGR1_AUTOSTOP_MASK;
+ writel(val, ®s->mcfgr1);
+ /* wait tx fifo ready */
+ result = bus_i2c_wait_for_tx_ready(bus);
+ if (result) {
+ debug("i2c: start wait for tx ready: 0x%x\n", result);
+ return result;
+ }
+ /* issue start command */
+ val = LPI2C_MTDR_CMD(0x4) | (addr << 0x1) | dir;
+ writel(val, ®s->mtdr);
+
+ return result;
+}
+static int bus_i2c_stop(struct udevice *bus)
+{
+ struct imx_lpi2c_reg *regs = (struct imx_lpi2c_reg *)dev_get_addr(bus);
+ lpi2c_status_t result = LPI2C_SUCESS;
+ u32 status;
+
+ result = bus_i2c_wait_for_tx_ready(bus);
+ if (result) {
+ debug("i2c: stop wait for tx ready: 0x%x\n", result);
+ return result;
+ }
+
+ /* send stop command */
+ writel(LPI2C_MTDR_CMD(0x2), ®s->mtdr);
+
+ while (result == LPI2C_SUCESS) {
+ status = readl(®s->msr);
+ result = imx_lpci2c_check_clear_error(bus);
+ /* stop detect flag */
+ if (status & LPI2C_MSR_SDF_MASK) {
+ /* clear stop flag */
+ status &= LPI2C_MSR_SDF_MASK;
+ writel(status, ®s->msr);
+ break;
+ }
+ }
+
+ return result;
+}
+
+static int bus_i2c_read(struct udevice *bus, u32 chip, u8 *buf, int len)
+{
+ lpi2c_status_t result = LPI2C_SUCESS;
+
+ result = bus_i2c_start(bus, chip, 1);
+ if (result)
+ return result;
+ result = bus_i2c_receive(bus, buf, len);
+ if (result)
+ return result;
+ result = bus_i2c_stop(bus);
+ if (result)
+ return result;
+
+ return result;
+}
+
+static int bus_i2c_write(struct udevice *bus, u32 chip, u8 *buf, int len)
+{
+ lpi2c_status_t result = LPI2C_SUCESS;
+
+ result = bus_i2c_start(bus, chip, 0);
+ if (result)
+ return result;
+ result = bus_i2c_send(bus, buf, len);
+ if (result)
+ return result;
+ result = bus_i2c_stop(bus);
+ if (result)
+ return result;
+
+ return result;
+}
+
+
+static int bus_i2c_set_bus_speed(struct udevice *bus, int speed)
+{
+ struct imx_lpi2c_reg *regs = (struct imx_lpi2c_reg *)dev_get_addr(bus);
+ u32 val;
+ u32 preescale = 0, best_pre = 0, clkhi = 0;
+ u32 best_clkhi = 0, abs_error = 0, rate;
+ u32 error = 0xffffffff;
+ u32 clock_rate;
+ bool mode;
+ int i;
+
+ clock_rate = imx_get_i2cclk(bus->seq + 4);
+ if (!clock_rate)
+ return -EPERM;
+
+ mode = (readl(®s->mcr) & LPI2C_MCR_MEN_MASK) >> LPI2C_MCR_MEN_SHIFT;
+ /* disable master mode */
+ val = readl(®s->mcr) & ~LPI2C_MCR_MEN_MASK;
+ writel(val | LPI2C_MCR_MEN(0), ®s->mcr);
+
+ for (preescale = 1; (preescale <= 128) &&
+ (error != 0); preescale = 2 * preescale) {
+ for (clkhi = 1; clkhi < 32; clkhi++) {
+ if (clkhi == 1)
+ rate = (clock_rate / preescale) / (1 + 3 + 2 + 2 / preescale);
+ else
+ rate = (clock_rate / preescale / (3 * clkhi + 2 + 2 / preescale));
+
+ abs_error = speed > rate ? speed - rate : rate - speed;
+
+ if (abs_error < error) {
+ best_pre = preescale;
+ best_clkhi = clkhi;
+ error = abs_error;
+ if (abs_error == 0)
+ break;
+ }
+ }
+ }
+
+ /* Standard, fast, fast mode plus and ultra-fast transfers. */
+ val = LPI2C_MCCR0_CLKHI(best_clkhi);
+ if (best_clkhi < 2)
+ val |= LPI2C_MCCR0_CLKLO(3) | LPI2C_MCCR0_SETHOLD(2) | LPI2C_MCCR0_DATAVD(1);
+ else
+ val |= LPI2C_MCCR0_CLKLO(2 * best_clkhi) | LPI2C_MCCR0_SETHOLD(best_clkhi) |
+ LPI2C_MCCR0_DATAVD(best_clkhi / 2);
+ writel(val, ®s->mccr0);
+
+ for (i = 0; i < 8; i++) {
+ if (best_pre == (1 << i)) {
+ best_pre = i;
+ break;
+ }
+ }
+
+ val = readl(®s->mcfgr1) & ~LPI2C_MCFGR1_PRESCALE_MASK;
+ writel(val | LPI2C_MCFGR1_PRESCALE(best_pre), ®s->mcfgr1);
+
+ if (mode) {
+ val = readl(®s->mcr) & ~LPI2C_MCR_MEN_MASK;
+ writel(val | LPI2C_MCR_MEN(1), ®s->mcr);
+ }
+
+ return 0;
+}
+
+static int bus_i2c_init(struct udevice *bus, int speed)
+{
+ struct imx_lpi2c_reg *regs = (struct imx_lpi2c_reg *)dev_get_addr(bus);
+ u32 val;
+ int ret;
+
+ /* reset peripheral */
+ writel(LPI2C_MCR_RST_MASK, ®s->mcr);
+ writel(0x0, ®s->mcr);
+ /* Disable Dozen mode */
+ writel(LPI2C_MCR_DBGEN(0) | LPI2C_MCR_DOZEN(1), ®s->mcr);
+ /* host request disable, active high, external pin */
+ val = readl(®s->mcfgr0);
+ val &= (~(LPI2C_MCFGR0_HREN_MASK | LPI2C_MCFGR0_HRPOL_MASK |
+ LPI2C_MCFGR0_HRSEL_MASK));
+ val |= LPI2C_MCFGR0_HRPOL(0x1);
+ writel(val, ®s->mcfgr0);
+ /* pincfg and ignore ack */
+ val = readl(®s->mcfgr1);
+ val &= ~(LPI2C_MCFGR1_PINCFG_MASK | LPI2C_MCFGR1_IGNACK_MASK);
+ val |= LPI2C_MCFGR1_PINCFG(0x0); /* 2 pin open drain */
+ val |= LPI2C_MCFGR1_IGNACK(0x0); /* ignore nack */
+ writel(val, ®s->mcfgr1);
+
+ ret = bus_i2c_set_bus_speed(bus, speed);
+
+ /* enable lpi2c in master mode */
+ val = readl(®s->mcr) & ~LPI2C_MCR_MEN_MASK;
+ writel(val | LPI2C_MCR_MEN(1), ®s->mcr);
+
+ debug("i2c : controller bus %d, speed %d:\n", bus->seq, speed);
+
+ return ret;
+}
+
+static int imx_lpi2c_probe_chip(struct udevice *bus, u32 chip,
+ u32 chip_flags)
+{
+ lpi2c_status_t result = LPI2C_SUCESS;
+
+ result = bus_i2c_start(bus, chip, 0);
+ if (result) {
+ bus_i2c_stop(bus);
+ bus_i2c_init(bus, 100000);
+ return result;
+ }
+
+ result = bus_i2c_stop(bus);
+ if (result) {
+ bus_i2c_init(bus, 100000);
+ return -result;
+ }
+
+ return result;
+}
+
+static int imx_lpi2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
+{
+ int ret = 0;
+
+ for (; nmsgs > 0; nmsgs--, msg++) {
+ debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
+ if (msg->flags & I2C_M_RD)
+ ret = bus_i2c_read(bus, msg->addr, msg->buf,
+ msg->len);
+ else {
+ ret = bus_i2c_write(bus, msg->addr, msg->buf,
+ msg->len);
+ if (ret)
+ break;
+ }
+ }
+
+ if (ret)
+ debug("i2c_write: error sending\n");
+
+ return ret;
+}
+
+static int imx_lpi2c_set_bus_speed(struct udevice *bus, unsigned int speed)
+{
+ return bus_i2c_set_bus_speed(bus, speed);
+}
+
+static int imx_lpi2c_probe(struct udevice *bus)
+{
+ struct imx_lpi2c_bus *i2c_bus = dev_get_priv(bus);
+ fdt_addr_t addr;
+ int ret;
+
+ i2c_bus->driver_data = dev_get_driver_data(bus);
+
+ addr = dev_get_addr(bus);
+ if (addr == FDT_ADDR_T_NONE)
+ return -ENODEV;
+
+ i2c_bus->base = addr;
+ i2c_bus->index = bus->seq;
+ i2c_bus->bus = bus;
+
+ /* power up i2c resource */
+ ret = init_i2c_power(bus->seq + 4);
+ if (ret) {
+ debug("init_i2c_power err = %d\n", ret);
+ return ret;
+ }
+
+ /* Enable clk, only i2c4-7 can be handled by A7 core */
+ ret = enable_i2c_clk(1, bus->seq + 4);
+ if (ret < 0)
+ return ret;
+
+ ret = bus_i2c_init(bus, 100000);
+ if (ret < 0)
+ return ret;
+
+ debug("i2c : controller bus %d at %lu , speed %d: ",
+ bus->seq, i2c_bus->base,
+ i2c_bus->speed);
+
+ return 0;
+}
+
+static const struct dm_i2c_ops imx_lpi2c_ops = {
+ .xfer = imx_lpi2c_xfer,
+ .probe_chip = imx_lpi2c_probe_chip,
+ .set_bus_speed = imx_lpi2c_set_bus_speed,
+};
+
+static const struct udevice_id imx_lpi2c_ids[] = {
+ { .compatible = "fsl,imx7ulp-lpi2c", },
+ {}
+};
+
+U_BOOT_DRIVER(imx_lpi2c) = {
+ .name = "imx_lpi2c",
+ .id = UCLASS_I2C,
+ .of_match = imx_lpi2c_ids,
+ .probe = imx_lpi2c_probe,
+ .priv_auto_alloc_size = sizeof(struct imx_lpi2c_bus),
+ .ops = &imx_lpi2c_ops,
+};
--
2.6.2
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