[U-Boot] [PATCHv2 1/2] armv8: Enable CPUECTLR.SMPEN for coherency

[Masahiro Yamada]

Hi.


2017-01-06 18:41 GMT+09:00 Zhiqiang Hou <Zhiqiang.Hou at nxp.com>:
> From: Mingkai Hu <mingkai.hu at nxp.com>
>
> For A53, data coherency is enabled only when the CPUECTLR.SMPEN bit is
> set. The SMPEN bit should be set before enabling the data cache.
> If not enabled, the cache is not coherent with other cores and
> data corruption could occur.
>
> For A57/A72, SMPEN bit enables the processor to receive instruction
> cache and TLB maintenance operations broadcast from other processors
> in the cluster. This bit should be set before enabling the caches and
> MMU, or performing any cache and TLB maintenance operations.
>
> Signed-off-by: Mingkai Hu <mingkai.hu at nxp.com>
> Signed-off-by: Gong Qianyu <Qianyu.Gong at nxp.com>
> Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski at gmail.com>
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou at nxp.com>
> ---
> V2:
>  - Revised the help information.
>
>  arch/arm/cpu/armv8/Kconfig | 18 ++++++++++++++++++
>  arch/arm/cpu/armv8/start.S | 11 +++++++++++
>  2 files changed, 29 insertions(+)
>
> diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig
> index 22dce88..472b2ba 100644
> --- a/arch/arm/cpu/armv8/Kconfig
> +++ b/arch/arm/cpu/armv8/Kconfig
> @@ -3,6 +3,24 @@ if ARM64
>  config ARMV8_MULTIENTRY
>          bool "Enable multiple CPUs to enter into U-Boot"
>
> +config ARMV8_SET_SMPEN
> +        bool "Enable data coherency with other cores in cluster"
> +        help
> +         Say Y here if there is not any trust firmware to set
> +         CPUECTLR_EL1.SMPEN bit before U-Boot.


I am a bit curious about this.
Are you planning to implement Trusted Firmware in the future?
It this option a temporary work-around until then?





-- 
Best Regards
Masahiro Yamada