[U-Boot] [v3 07/30] arm: socfpga: arria10: add socfpga_arria10_defconfig

[Chee Tien Fong]

From: Tien Fong Chee <tien.fong.chee at intel.com>

Add a defconfig file for Arria10, which does not include enabling SPL.

Signed-off-by: Dinh Nguyen <dinguyen at opensource.altera.com>
Signed-off-by: Tien Fong Chee <tien.fong.chee at intel.com>
Acked-by: Marek Vasut <marex at denx.de>
Cc: Marek Vasut <marex at denx.de>
Cc: Dinh Nguyen <dinguyen at kernel.org>
Cc: Chin Liang See <chin.liang.see at intel.com>
Cc: Tien Fong <skywindctf at gmail.com>
---
 configs/socfpga_arria10_defconfig |   16 ++++++++++++++++
 1 files changed, 16 insertions(+), 0 deletions(-)
 create mode 100644 configs/socfpga_arria10_defconfig

diff --git a/configs/socfpga_arria10_defconfig b/configs/socfpga_arria10_defconfig
new file mode 100644
index 0000000..422261b
--- /dev/null
+++ b/configs/socfpga_arria10_defconfig
@@ -0,0 +1,16 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SOCFPGA=y
+CONFIG_TARGET_SOCFPGA_ARRIA10=y
+CONFIG_DM_GPIO=y
+CONFIG_TARGET_SOCFPGA_ARRIA10_SOCDK=y
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_DWAPB_GPIO=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_SYS_NS16550=y
+CONFIG_CADENCE_QSPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_DM_MMC=y
-- 
1.7.7.4