[U-Boot] [PATCH 8/8] clk: zynq: Add optional ethernet emio clock source support

[Michal Simek]

On 4.1.2017 13:27, stefan.herbrechtsmeier at weidmueller.com wrote:
> From: Stefan Herbrechtsmeier <stefan.herbrechtsmeier at weidmueller.com>
> 
> Add support for the optional ethernet emio clock source to the zynq
> clock framework driver.
> 
> Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier at weidmueller.com>
> 
> ---
> 
>  drivers/clk/clk_zynq.c | 33 +++++++++++++++++++++++++++++++--
>  1 file changed, 31 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/clk/clk_zynq.c b/drivers/clk/clk_zynq.c
> index d276155..6f1448d 100644
> --- a/drivers/clk/clk_zynq.c
> +++ b/drivers/clk/clk_zynq.c
> @@ -53,6 +53,9 @@ enum zynq_clk_rclk {mio_clk, emio_clk};
>  
>  struct zynq_clk_priv {
>  	ulong ps_clk_freq;
> +#ifndef CONFIG_SPL_BUILD
> +	struct clk gem_emio_clk[2];
> +#endif
>  };
>  
>  static void *zynq_clk_get_register(enum zynq_clk id)
> @@ -284,10 +287,16 @@ static ulong zynq_clk_get_peripheral_rate(struct zynq_clk_priv *priv,
>  #ifndef CONFIG_SPL_BUILD
>  static ulong zynq_clk_get_gem_rate(struct zynq_clk_priv *priv, enum zynq_clk id)
>  {
> +	struct clk *parent;
> +
>  	if (zynq_clk_get_gem_rclk(id) == mio_clk)
>  		return zynq_clk_get_peripheral_rate(priv, id, true);
>  
> -	return 0;
> +	parent = &priv->gem_emio_clk[id - gem0_clk];
> +	if (parent)
> +		return clk_get_rate(parent);
> +
> +	return -ENXIO;
>  }
>  
>  static unsigned long zynq_clk_calc_peripheral_two_divs(
> @@ -354,10 +363,16 @@ static ulong zynq_clk_set_peripheral_rate(struct zynq_clk_priv *priv,
>  static ulong zynq_clk_set_gem_rate(struct zynq_clk_priv *priv, enum zynq_clk id,
>  				   ulong rate)
>  {
> +	struct clk *parent;
> +
>  	if (zynq_clk_get_gem_rclk(id) == mio_clk)
>  		return zynq_clk_set_peripheral_rate(priv, id, rate, true);
>  
> -	return 0;
> +	parent = &priv->gem_emio_clk[id - gem0_clk];
> +	if (parent)
> +		return clk_set_rate(parent, rate);
> +
> +	return -ENXIO;
>  }
>  #endif
>  
> @@ -447,6 +462,20 @@ static struct clk_ops zynq_clk_ops = {
>  static int zynq_clk_probe(struct udevice *dev)
>  {
>  	struct zynq_clk_priv *priv = dev_get_priv(dev);
> +#ifndef CONFIG_SPL_BUILD
> +	unsigned int i;
> +	char name[16];
> +	int ret;
> +
> +	for (i = 0; i < 2; i++) {
> +		sprintf(name, "gem%d_emio_clk", i);
> +		ret = clk_get_by_name(dev, name, &priv->gem_emio_clk[i]);
> +		if (ret < 0 && ret != -FDT_ERR_NOTFOUND) {
> +			dev_err(dev, "failed to get %s clock\n", name);
> +			return ret;
> +		}
> +	}
> +#endif
>  
>  	priv->ps_clk_freq = fdtdec_get_uint(gd->fdt_blob, dev->of_offset,
>  					    "ps-clk-frequency", 33333333UL);
> 

Ah ok. Here it is emio stuff for ethernet.

Thanks,
Michal

-- 
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP SoCs


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