[U-Boot] [PATCH 1/8] net: zynq: Don't overwrite gem_rclk_ctrl with default value

[Michal Simek]

+siva

On 10.1.2017 15:28, Stefan.Herbrechtsmeier at weidmueller.com wrote:
> Hi Michal,
> 
>> -----Ursprüngliche Nachricht-----
>> Von: Michal Simek [mailto:monstr at monstr.eu]
>> Gesendet: Dienstag, 10. Januar 2017 14:53
>> An: Herbrechtsmeier, Stefan; u-boot at lists.denx.de
>> Cc: Herbrechtsmeier, Stefan; Michal Simek; Jagan Teki; Albert Aribaud;
>> Joe Hershberger; Mike Looijmans
>> Betreff: Re: [PATCH 1/8] net: zynq: Don't overwrite gem_rclk_ctrl with
>> default value
>>
>> On 4.1.2017 13:27, stefan.herbrechtsmeier at weidmueller.com wrote:
>>> From: Stefan Herbrechtsmeier <stefan.herbrechtsmeier at weidmueller.de>
>>>
>>> The gem[0-1]_rclk_ctrl registers control the source of the rx clock,
>>> control and data signals and configure via ps7_init function. Don't
>>> overwrite the register with the default value.
>>
>> TBH I don't think this is a win for us to relate on ps7_init
>> configuration. There are a lot of things there but I would like to
>> control this in this sw instead of psu_init.
> 
> At the moment the ps7_init only touch the register if the board doesn't use the default configuration. U-boot overwrite the register with the default value if 'xlnx,emio' isn't set in the device tree. It doesn't change the value to gem_rclk_ctrl if 'xlnx,emio' is set.
> 
> At the moment the clock configuration is managed by the ps7_init and only the gem_rclk_ctrl configuration is overwritten by u-boot. I don't think it is correct do overwrite some part of the clock tree configuration which is generated by Xilinx tools.

ok.

Siva: I don't have testcase for emio or any hw design to test this.
Do you have something which we can check?

Thanks,
Michal

-- 
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP SoCs


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