[U-Boot] [PATCH v2 33/63] x86: Add cpu code for x86_64

[Bin Meng]

Hi Simon,

On Sun, Nov 20, 2016 at 4:25 AM, Simon Glass <sjg at chromium.org> wrote:
> There is not much needed at present, but set up a separate directory to put
> this code as it grows.
>
> Signed-off-by: Simon Glass <sjg at chromium.org>
> ---
>
> Changes in v2: None
>
>  arch/x86/cpu/Makefile            |  4 +++-
>  arch/x86/cpu/x86_64/Makefile     |  6 ++++++
>  arch/x86/cpu/x86_64/cpu.c        | 35 +++++++++++++++++++++++++++++++++++
>  arch/x86/cpu/x86_64/interrupts.c | 30 ++++++++++++++++++++++++++++++
>  4 files changed, 74 insertions(+), 1 deletion(-)
>  create mode 100644 arch/x86/cpu/x86_64/Makefile
>  create mode 100644 arch/x86/cpu/x86_64/cpu.c
>  create mode 100644 arch/x86/cpu/x86_64/interrupts.c
>
> diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile
> index 41ad481..7f89ff0 100644
> --- a/arch/x86/cpu/Makefile
> +++ b/arch/x86/cpu/Makefile
> @@ -38,6 +38,8 @@ obj-$(CONFIG_PCI) += pci.o
>  obj-$(CONFIG_SMP) += sipi_vector.o
>  obj-y += turbo.o
>
> -ifeq ($(CONFIG_$(SPL_)X86_64),)
> +ifeq ($(CONFIG_$(SPL_)X86_64),y)
> +obj-y += x86_64/
> +else
>  obj-y += i386/
>  endif
> diff --git a/arch/x86/cpu/x86_64/Makefile b/arch/x86/cpu/x86_64/Makefile
> new file mode 100644
> index 0000000..4b06386
> --- /dev/null
> +++ b/arch/x86/cpu/x86_64/Makefile
> @@ -0,0 +1,6 @@
> +#
> +# (C) Copyright 2016 Google, Inc
> +# Written by Simon Glass <sjg at chromium.org>
> +#
> +
> +obj-y += cpu.o interrupts.o
> diff --git a/arch/x86/cpu/x86_64/cpu.c b/arch/x86/cpu/x86_64/cpu.c
> new file mode 100644
> index 0000000..c1d3788
> --- /dev/null
> +++ b/arch/x86/cpu/x86_64/cpu.c
> @@ -0,0 +1,35 @@
> +/*
> + * (C) Copyright 2016 Google, Inc
> + * Written by Simon Glass <sjg at chromium.org>
> + *
> + * SPDX-License-Identifier:    GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <debug_uart.h>

nits: <debug_uart.h> is not needed

> +
> +int cpu_has_64bit(void)
> +{
> +       return true;
> +}
> +
> +void enable_caches(void)
> +{
> +       /* Not implemented */
> +}
> +
> +void disable_caches(void)
> +{
> +       /* Not implemented */
> +}
> +
> +int dcache_status(void)
> +{
> +       return true;
> +}
> +
> +int x86_mp_init(void)
> +{
> +       /* Not implemented */
> +       return 0;
> +}
> diff --git a/arch/x86/cpu/x86_64/interrupts.c b/arch/x86/cpu/x86_64/interrupts.c
> new file mode 100644
> index 0000000..d814b6a
> --- /dev/null
> +++ b/arch/x86/cpu/x86_64/interrupts.c
> @@ -0,0 +1,30 @@
> +/*
> + * (C) Copyright 2016 Google, Inc
> + * Written by Simon Glass <sjg at chromium.org>
> + *
> + * SPDX-License-Identifier:    GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <asm/processor-flags.h>
> +
> +void enable_interrupts(void)
> +{
> +       asm("sti\n");
> +}
> +
> +int disable_interrupts(void)
> +{
> +       long flags;
> +
> +       asm volatile ("pushfq ; popq %0 ; cli\n" : "=g" (flags) : );
> +
> +       return flags & X86_EFLAGS_IF;
> +}
> +
> +int interrupt_init(void)
> +{
> +       /* Nothing to do - this was already done in SPL */
> +       return 0;
> +}
> +

nits: this line is not needed

Other than that,
Reviewed-by: Bin Meng <bmeng.cn at gmail.com>