[U-Boot] [PATCH 2/3] CLK: OMAP: PCIE: Provide support for PCIE DPLL configuration

[Lukasz Majewski]

New function - configure_pcie_dpll() - has been added to allow setting up
the PCIe DPLL clock (1500 MHz).

Signed-off-by: Lukasz Majewski <lukma at denx.de>
---
 arch/arm/cpu/armv7/omap-common/clocks-common.c | 22 ++++++++++++++++++++++
 arch/arm/include/asm/omap_common.h             |  2 ++
 2 files changed, 24 insertions(+)

diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c
index 9b97583..56476bf 100644
--- a/arch/arm/cpu/armv7/omap-common/clocks-common.c
+++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c
@@ -208,6 +208,17 @@ static const struct dpll_params *get_gmac_dpll_params
 }
 #endif
 
+static const struct dpll_params *get_pcie_dpll_params
+			(struct dplls const *dpll_data)
+{
+	u32 sysclk_ind = get_sys_clk_index();
+
+	if (!dpll_data->pcie)
+		return NULL;
+
+	return &dpll_data->pcie[sysclk_ind];
+}
+
 static void do_setup_dpll(u32 const base, const struct dpll_params *params,
 				u8 lock, char *dpll)
 {
@@ -302,6 +313,17 @@ u32 omap_ddr_clk(void)
 	return ddr_clk;
 }
 
+void configure_pcie_dpll(void)
+{
+	const struct dpll_params *params;
+
+	params = get_pcie_dpll_params(*dplls_data);
+
+	do_setup_dpll((*prcm)->cm_clkmode_dpll_pcie_ref, params, DPLL_LOCK,
+		      "pcie");
+	debug("PCIE DPLL locked\n");
+}
+
 /*
  * Lock MPU dpll
  *
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
index cc40ee9..bb74321 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -612,6 +612,8 @@ void enable_basic_uboot_clocks(void);
 void enable_usb_clocks(int index);
 void disable_usb_clocks(int index);
 
+void configure_pcie_dpll(void);
+
 void scale_vcores(struct vcores_data const *);
 u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic);
 void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic);
-- 
2.1.4