[U-Boot] [PATCHv2 1/4] kconfig: armv8: move armv8 sec_firmware CONFIG_* to Kconfig

[Zhiqiang Hou]

From: Hou Zhiqiang <Zhiqiang.Hou at nxp.com>

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou at nxp.com>
---
V2:
 - Generate the patch base on the latest code.

 arch/arm/cpu/armv8/Kconfig            | 33 +++++++++++++++++++++++++++++++++
 arch/arm/cpu/armv8/Makefile           |  2 +-
 arch/arm/cpu/armv8/sec_firmware_asm.S |  4 ++--
 include/configs/ls1043ardb.h          |  3 ---
 include/configs/ls1046ardb.h          |  4 ----
 5 files changed, 36 insertions(+), 10 deletions(-)

diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig
index 22dce88..2ee5782 100644
--- a/arch/arm/cpu/armv8/Kconfig
+++ b/arch/arm/cpu/armv8/Kconfig
@@ -21,6 +21,39 @@ config ARMV8_SPIN_TABLE
 	    - Reserve the code for the spin-table and the release address
 	      via a /memreserve/ region in the Device Tree.
 
+menu "ARMv8 secure monitor firmware"
+config ARMV8_SEC_FIRMWARE_SUPPORT
+	bool "Enable ARMv8 secure monitor firmware framework support"
+	select OF_LIBFDT
+	select FIT
+	help
+	  This framework is aimed at making secure monitor firmware load
+	  process brief.
+	  Note: Only FIT format image is supported.
+	  You should prepare and provide the below information:
+	    - Address of secure firmware.
+	    - Address to hold the return address from secure firmware.
+	    - Secure firmware FIT image related information.
+	      Such as: SEC_FIRMWARE_FIT_IMAGE and SEC_FIRMEWARE_FIT_CNF_NAME
+	    - The target exception level that secure monitor firmware will
+	      return to.
+
+config SPL_ARMV8_SEC_FIRMWARE_SUPPORT
+	bool "Enable ARMv8 secure monitor firmware framework support for SPL"
+	select SPL_OF_LIBFDT
+	select SPL_FIT
+	help
+	  Say Y here to support this framework in SPL phase.
+
+config ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT
+	bool "ARMv8 secure monitor firmware ERET address byteorder swap"
+	depends on ARMV8_SEC_FIRMWARE_SUPPORT || SPL_ARMV8_SEC_FIRMWARE_SUPPORT
+	help
+	  Say Y here when the endianness of the register or memory holding the
+	  Secure firmware exception return address is different with core's.
+
+endmenu
+
 config PSCI_RESET
 	bool "Use PSCI for reset and shutdown"
 	default y
diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile
index 28ba786..1f1de4a 100644
--- a/arch/arm/cpu/armv8/Makefile
+++ b/arch/arm/cpu/armv8/Makefile
@@ -19,7 +19,7 @@ obj-y	+= cpu-dt.o
 ifndef CONFIG_SPL_BUILD
 obj-$(CONFIG_ARMV8_SPIN_TABLE) += spin_table.o spin_table_v8.o
 endif
-obj-$(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT) += sec_firmware.o sec_firmware_asm.o
+obj-$(CONFIG_$(SPL_)ARMV8_SEC_FIRMWARE_SUPPORT) += sec_firmware.o sec_firmware_asm.o
 
 obj-$(CONFIG_FSL_LAYERSCAPE) += fsl-layerscape/
 obj-$(CONFIG_S32V234) += s32v234/
diff --git a/arch/arm/cpu/armv8/sec_firmware_asm.S b/arch/arm/cpu/armv8/sec_firmware_asm.S
index 903195d..6bae15d 100644
--- a/arch/arm/cpu/armv8/sec_firmware_asm.S
+++ b/arch/arm/cpu/armv8/sec_firmware_asm.S
@@ -23,12 +23,12 @@ WEAK(_sec_firmware_entry)
 	/* Set exception return address hold pointer */
         adr	x4, 1f
         mov	x3, x4
-#ifdef SEC_FIRMWARE_ERET_ADDR_REVERT
+#ifdef CONFIG_ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT
         rev	w3, w3
 #endif
         str	w3, [x1]
         lsr	x3, x4, #32
-#ifdef SEC_FIRMWARE_ERET_ADDR_REVERT
+#ifdef CONFIG_ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT
         rev	w3, w3
 #endif
         str	w3, [x2]
diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h
index 71c26bd..cc9371a 100644
--- a/include/configs/ls1043ardb.h
+++ b/include/configs/ls1043ardb.h
@@ -10,9 +10,6 @@
 #include "ls1043a_common.h"
 
 #if defined(CONFIG_FSL_LS_PPA)
-#define CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
-#define SEC_FIRMWARE_ERET_ADDR_REVERT
-
 #define CONFIG_SYS_LS_PPA_FW_IN_XIP
 #ifdef CONFIG_SYS_LS_PPA_FW_IN_XIP
 #define	CONFIG_SYS_LS_PPA_FW_ADDR	0x60500000
diff --git a/include/configs/ls1046ardb.h b/include/configs/ls1046ardb.h
index 2fe8fc1..8ede24c 100644
--- a/include/configs/ls1046ardb.h
+++ b/include/configs/ls1046ardb.h
@@ -10,10 +10,6 @@
 #include "ls1046a_common.h"
 
 #if defined(CONFIG_FSL_LS_PPA)
-#define CONFIG_ARMV8_PSCI
-#define CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
-#define CONFIG_SYS_LS_PPA_DRAM_BLOCK_MIN_SIZE		(1UL * 1024 * 1024)
-
 #define CONFIG_SYS_LS_PPA_FW_IN_XIP
 #ifdef CONFIG_SYS_LS_PPA_FW_IN_XIP
 #define	CONFIG_SYS_LS_PPA_FW_ADDR	0x40500000
-- 
2.1.0.27.g96db324