[U-Boot] [u-boot] AR8033 SerDes Test and System Mode Control setting issue

[Ken.Lin]

Hi Joe and Mugunthan,

We encountered the voltage peak issue while doing the IEEE PHY conformance test, which has to do with the AR8033 register (SetDes Test and System Mode Control) setting in u-boot.
In your commit change info, you tried to enable tx clock delay by setting bit 8 to 1 (filling in 0x100, setting the reserved bits to 0) for solving the auto negotiation failure issue.
https://patchwork.ozlabs.org/patch/681801/

After we checked with Qualcomm (Atheros) and they responded that on their platform, the register should be set to 0x2C47 (for the reserved bits) and this would solve the voltage peak issue we experienced.
Could you please help check if it's appropriate to set the reserved bits according to Qualcomm's setting since your commit breaks the original setting (see https://community.nxp.com/message/868898 for more details info)?
Please let me know if you have any suggestions/comments on this.

Thank you

Cheers,
Ken Lin


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