[U-Boot] [PATCHv2 1/2] armv8: Enable CPUECTLR.SMPEN for coherency

[york sun]

On 01/06/2017 01:54 AM, Zhiqiang Hou wrote:
> From: Mingkai Hu <mingkai.hu at nxp.com>
>
> For A53, data coherency is enabled only when the CPUECTLR.SMPEN bit is
> set. The SMPEN bit should be set before enabling the data cache.
> If not enabled, the cache is not coherent with other cores and
> data corruption could occur.
>
> For A57/A72, SMPEN bit enables the processor to receive instruction
> cache and TLB maintenance operations broadcast from other processors
> in the cluster. This bit should be set before enabling the caches and
> MMU, or performing any cache and TLB maintenance operations.
>
> Signed-off-by: Mingkai Hu <mingkai.hu at nxp.com>
> Signed-off-by: Gong Qianyu <Qianyu.Gong at nxp.com>
> Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski at gmail.com>
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou at nxp.com>
> ---
> V2:
>  - Revised the help information.
>

This set is applied to fsl-qoriq master, awaiting upstream. Thanks.

York