[U-Boot] [PATCHv5 1/2] armv8/fsl-lsch2: refactor the clock system initialization

[york sun]

On 01/10/2017 12:57 AM, Zhiqiang Hou wrote:
> From: Hou Zhiqiang <Zhiqiang.Hou at nxp.com>
>
> Up to now, there are 3 kind of SoCs under Layerscape Chassis 2,
> like LS1043A, LS1046A and LS1012A. But the clocks tree has a
> lot of differences, for instance, the IP modules have different
> dividers to derive its clock from Platform PLL. And the core
> cluster PLL and platform PLL maybe have different reference
> clocks, such as LS1012A. Another problem is which clock/PLL
> should be described by sys_info->freq_systembus, it is confused
> in Layerscape Chissis 2.
>
> This patch is to bind the sys_info->freq_systembus to the Platform
> PLL, and handle the different divider of IP modules separately
> between different SoCs, and separate reference clocks of core
> cluster PLL and platform PLL.
>
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou at nxp.com>
> ---
> V5:
>  - Correct the eSDHC controller clock getting.
>

This set is applied to fsl-qoriq master, awaiting upstream. Thanks.

York