[U-Boot] ARM - cache and alignment

[Tom Rini]

On Mon, Jan 16, 2017 at 02:29:21PM +0100, Jean-Jacques Hiblot wrote:

> Tom, Marek
> 
> At the moment, whenever an unaligned address is used in cache
> operations (invalidate_dcache_range, or flush_dcache_range), the
> whole request is discarded  for am926ejs. for armV7 or armV8 only
> the aligned part is maintained. This is probably what is causing the
> bug addressed in 8133f43d1cd. There are a lot of unaligned buffers
> used in DMA operations and for all of them, we're possibly handling
> the cached partially or not at all. I've seen this when using the
> environment from a file stored in a FAT partition. commit
> 8133f43d1cd addresses this by using a bounce buffer at the FAT level
> but it's only one of many cases.
> 
> I think we can do better with unaligned cache operations:

My current feeling here is that the main problems here, with respect to
buffers not being aligned, is that as we move forward with DM changes we
can push this up a level and it will be harder to get this wrong.
Patches to fix problems found in the mean time are welcome.

-- 
Tom
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