[U-Boot] [PATCH v4 08/28] arm: socfpga: arria10: add config option build for arria10

[Marek Vasut]

On 01/10/2017 06:20 AM, Chee Tien Fong wrote:
> From: Tien Fong Chee <tien.fong.chee at intel.com>

Commit message missing.

> Signed-off-by: Dinh Nguyen <dinguyen at opensource.altera.com>
> Signed-off-by: Tien Fong Chee <tien.fong.chee at intel.com>
> Cc: Marek Vasut <marex at denx.de>
> Cc: Dinh Nguyen <dinguyen at kernel.org>
> Cc: Chin Liang See <chin.liang.see at intel.com>
> Cc: Tien Fong <skywindctf at gmail.com>
> ---
>  arch/arm/Kconfig              |  4 ++--
>  arch/arm/mach-socfpga/Kconfig | 10 ++++++++++
>  2 files changed, 12 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 0ed36cd..80c5992 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -561,9 +561,9 @@ config ARCH_SNAPDRAGON
>  config ARCH_SOCFPGA
>  	bool "Altera SOCFPGA family"
>  	select CPU_V7
> -	select SUPPORT_SPL
> +	select SUPPORT_SPL if !TARGET_SOCFPGA_ARRIA10
>  	select OF_CONTROL
> -	select SPL_OF_CONTROL
> +	select SPL_OF_CONTROL if !TARGET_SOCFPGA_ARRIA10

What's this about ? SPL is broken on A10 ?

>  	select DM
>  	select DM_SPI_FLASH
>  	select DM_SPI
> diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
> index 6991af8..d9a5178 100644
> --- a/arch/arm/mach-socfpga/Kconfig
> +++ b/arch/arm/mach-socfpga/Kconfig
> @@ -31,6 +31,9 @@ config TARGET_SOCFPGA_ARRIA5
>  	bool
>  	select TARGET_SOCFPGA_GEN5
>  
> +config TARGET_SOCFPGA_ARRIA10
> +	bool
> +
>  config TARGET_SOCFPGA_CYCLONE5
>  	bool
>  	select TARGET_SOCFPGA_GEN5
> @@ -50,6 +53,10 @@ config TARGET_SOCFPGA_CYCLONE5_SOCDK
>  	bool "Altera SOCFPGA SoCDK (Cyclone V)"
>  	select TARGET_SOCFPGA_CYCLONE5
>  
> +config TARGET_SOCFPGA_ARRIA10_SOCDK

Keep the list sorted , Arria10 goes in front of Arria 5.

> +	bool "Altera SOCFPGA SoCDK (Arria 10)"
> +	select TARGET_SOCFPGA_ARRIA10
> +
>  config TARGET_SOCFPGA_DENX_MCVEVK
>  	bool "DENX MCVEVK (Cyclone V)"
>  	select TARGET_SOCFPGA_CYCLONE5
> @@ -86,6 +93,7 @@ endchoice
>  
>  config SYS_BOARD
>  	default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
> +	default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
>  	default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
>  	default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
>  	default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
> @@ -98,6 +106,7 @@ config SYS_BOARD
>  
>  config SYS_VENDOR
>  	default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
> +	default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK
>  	default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
>  	default "denx" if TARGET_SOCFPGA_DENX_MCVEVK
>  	default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
> @@ -111,6 +120,7 @@ config SYS_SOC
>  
>  config SYS_CONFIG_NAME
>  	default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
> +	default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
>  	default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
>  	default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
>  	default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
> 


-- 
Best regards,
Marek Vasut