[U-Boot] [PATCH v4 23/28] arm: socfpga: arria10: Added drivers for Arria10 Reset Manager
Marek Vasut
marex at denx.de
Mon Jan 23 05:13:33 CET 2017
On 01/10/2017 06:20 AM, Chee Tien Fong wrote:
> From: Tien Fong Chee <tien.fong.chee at intel.com>
>
> Drivers for reset manager is restructured such that common functions,
> gen5 drivers and Arria10 drivers are moved to reset_manager.c,
> reset_manager_gen5.c and reset_manager_arria10.c respectively.
>
> Signed-off-by: Tien Fong Chee <tien.fong.chee at intel.com>
> Cc: Marek Vasut <marex at denx.de>
> Cc: Dinh Nguyen <dinguyen at kernel.org>
> Cc: Chin Liang See <chin.liang.see at intel.com>
> Cc: Tien Fong <skywindctf at gmail.com>
> ---
> arch/arm/mach-socfpga/Makefile | 16 +-
> arch/arm/mach-socfpga/include/mach/reset_manager.h | 155 ++++++--
> arch/arm/mach-socfpga/reset_manager.c | 112 +-----
> arch/arm/mach-socfpga/reset_manager_arria10.c | 407 +++++++++++++++++++++
> .../{reset_manager.c => reset_manager_gen5.c} | 94 ++---
> 5 files changed, 570 insertions(+), 214 deletions(-)
> create mode 100644 arch/arm/mach-socfpga/reset_manager_arria10.c
> copy arch/arm/mach-socfpga/{reset_manager.c => reset_manager_gen5.c} (58%)
>
> diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
> index 809cd47..b8fcf6e 100644
> --- a/arch/arm/mach-socfpga/Makefile
> +++ b/arch/arm/mach-socfpga/Makefile
> @@ -2,21 +2,27 @@
> # (C) Copyright 2000-2003
> # Wolfgang Denk, DENX Software Engineering, wd at denx.de.
> #
> -# Copyright (C) 2012 Altera Corporation <www.altera.com>
> +# Copyright (C) 2012-2016 Altera Corporation <www.altera.com>
> #
> # SPDX-License-Identifier: GPL-2.0+
> #
>
> obj-y += misc.o timer.o reset_manager.o system_manager.o clock_manager.o \
> fpga_manager.o board.o
> +obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += reset_manager_arria10.o
> +obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += scan_manager.o wrap_pll_config.o \
> + reset_manager_gen5.o
>
> -obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
> +ifdef CONFIG_SPL_BUILD
> +obj-y += spl.o
> +obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += freeze_controller.o wrap_iocsr_config.o \
> + wrap_pinmux_config.o wrap_sdram_config.o
> +endif
>
> +ifdef CONFIG_TARGET_SOCFPGA_GEN5
> # QTS-generated config file wrappers
> -obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += scan_manager.o wrap_pll_config.o
> -obj-$(CONFIG_SPL_BUILD) += wrap_iocsr_config.o wrap_pinmux_config.o \
> - wrap_sdram_config.o
> CFLAGS_wrap_iocsr_config.o += -I$(srctree)/board/$(BOARDDIR)
> CFLAGS_wrap_pinmux_config.o += -I$(srctree)/board/$(BOARDDIR)
> CFLAGS_wrap_pll_config.o += -I$(srctree)/board/$(BOARDDIR)
> CFLAGS_wrap_sdram_config.o += -I$(srctree)/board/$(BOARDDIR)
> +endif
> diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h b/arch/arm/mach-socfpga/include/mach/reset_manager.h
> index 6225118..13f9731 100644
> --- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
> +++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
> @@ -1,5 +1,5 @@
> /*
> - * Copyright (C) 2012 Altera Corporation <www.altera.com>
> + * Copyright (C) 2012-2016 Altera Corporation <www.altera.com>
> *
> * SPDX-License-Identifier: GPL-2.0+
> */
> @@ -7,15 +7,27 @@
> #ifndef _RESET_MANAGER_H_
> #define _RESET_MANAGER_H_
>
> +/* Common function prototypes */
> void reset_cpu(ulong addr);
> -void reset_deassert_peripherals_handoff(void);
> -
> void socfpga_bridges_reset(int enable);
> -
> void socfpga_per_reset(u32 reset, int set);
> void socfpga_per_reset_all(void);
>
> #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> +void reset_deassert_peripherals_handoff(void);
> +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> +void watchdog_disable(void);
> +void reset_deassert_noc_ddr_scheduler(void);
> +int is_wdt_in_reset(void);
> +void emac_manage_reset(ulong emacbase, uint state);
> +int reset_deassert_bridges_handoff(void);
> +void reset_assert_fpga_connected_peripherals(void);
> +void reset_deassert_osc1wd0(void);
> +void reset_assert_uart(void);
> +void reset_deassert_uart(void);
> +#endif
> +
> +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> struct socfpga_reset_manager {
> u32 status;
> u32 ctrl;
> @@ -29,40 +41,40 @@ struct socfpga_reset_manager {
> u32 padding2[12];
> u32 tstscratch;
> };
> -#else
> +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> struct socfpga_reset_manager {
> - u32 stat;
> - u32 ramstat;
> - u32 miscstat;
> - u32 ctrl;
> - u32 hdsken;
> - u32 hdskreq;
> - u32 hdskack;
> - u32 counts;
> - u32 mpu_mod_reset;
> - u32 per_mod_reset; /* stated as per0_mod_reset in A10 datasheet */
> - u32 per2_mod_reset; /* stated as per1_mod_reset in A10 datasheet */
> - u32 brg_mod_reset;
> - u32 misc_mod_reset; /* stated as sys_mod_reset in A10 datasheet */
> - u32 coldmodrst;
> - u32 nrstmodrst;
> - u32 dbgmodrst;
> - u32 mpuwarmmask;
> - u32 per0warmmask;
> - u32 per1warmmask;
> - u32 brgwarmmask;
> - u32 syswarmmask;
> - u32 nrstwarmmask;
> - u32 l3warmmask;
> - u32 tststa;
> - u32 tstscratch;
> - u32 hdsktimeout;
> - u32 hmcintr;
> - u32 hmcintren;
> - u32 hmcintrens;
> - u32 hmcintrenr;
> - u32 hmcgpout;
> - u32 hmcgpin;
> + uint32_t stat;
This is NOT userspace, retain u32 !
> + uint32_t ramstat;
> + uint32_t miscstat;
> + uint32_t ctrl;
> + uint32_t hdsken;
> + uint32_t hdskreq;
> + uint32_t hdskack;
> + uint32_t counts;
> + uint32_t mpumodrst;
> + uint32_t per0modrst;
> + uint32_t per1modrst;
> + uint32_t brgmodrst;
> + uint32_t sysmodrst;
> + uint32_t coldmodrst;
> + uint32_t nrstmodrst;
> + uint32_t dbgmodrst;
> + uint32_t mpuwarmmask;
> + uint32_t per0warmmask;
> + uint32_t per1warmmask;
> + uint32_t brgwarmmask;
> + uint32_t syswarmmask;
> + uint32_t nrstwarmmask;
> + uint32_t l3warmmask;
> + uint32_t tststa;
> + uint32_t tstscratch;
> + uint32_t hdsktimeout;
> + uint32_t hmcintr;
> + uint32_t hmcintren;
> + uint32_t hmcintrens;
> + uint32_t hmcintrenr;
> + uint32_t hmcgpout;
> + uint32_t hmcgpin;
> };
> #endif
>
> @@ -113,7 +125,7 @@ struct socfpga_reset_manager {
> #define RSTMGR_SDMMC RSTMGR_DEFINE(1, 22)
> #define RSTMGR_DMA RSTMGR_DEFINE(1, 28)
> #define RSTMGR_SDR RSTMGR_DEFINE(1, 29)
> -#else
> +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> /*
> * SocFPGA Arria10 reset IDs, bank mapping is as follows:
> * 0 ... mpumodrst
> @@ -144,4 +156,71 @@ struct socfpga_reset_manager {
> /* Create a human-readable reference to SoCFPGA reset. */
> #define SOCFPGA_RESET(_name) RSTMGR_##_name
>
> +/* Create a human-readable reference to SoCFPGA reset. */
> +#define SOCFPGA_RESET(_name) RSTMGR_##_name
> +
> +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> +#define ALT_RSTMGR_CTL_SWWARMRSTREQ_SET_MSK 0x00000002
Use BIT() macro instead.
> +#define ALT_RSTMGR_PER0MODRST_EMAC0_SET_MSK 0x00000001
> +#define ALT_RSTMGR_PER0MODRST_EMAC1_SET_MSK 0x00000002
> +#define ALT_RSTMGR_PER0MODRST_EMAC2_SET_MSK 0x00000004
> +#define ALT_RSTMGR_PER0MODRST_USB0_SET_MSK 0x00000008
> +#define ALT_RSTMGR_PER0MODRST_USB1_SET_MSK 0x00000010
> +#define ALT_RSTMGR_PER0MODRST_NAND_SET_MSK 0x00000020
> +#define ALT_RSTMGR_PER0MODRST_QSPI_SET_MSK 0x00000040
> +#define ALT_RSTMGR_PER0MODRST_SDMMC_SET_MSK 0x00000080
> +#define ALT_RSTMGR_PER0MODRST_EMACECC0_SET_MSK 0x00000100
> +#define ALT_RSTMGR_PER0MODRST_EMACECC1_SET_MSK 0x00000200
> +#define ALT_RSTMGR_PER0MODRST_EMACECC2_SET_MSK 0x00000400
> +#define ALT_RSTMGR_PER0MODRST_USBECC0_SET_MSK 0x00000800
> +#define ALT_RSTMGR_PER0MODRST_USBECC1_SET_MSK 0x00001000
> +#define ALT_RSTMGR_PER0MODRST_NANDECC_SET_MSK 0x00002000
> +#define ALT_RSTMGR_PER0MODRST_QSPIECC_SET_MSK 0x00004000
> +#define ALT_RSTMGR_PER0MODRST_SDMMCECC_SET_MSK 0x00008000
> +#define ALT_RSTMGR_PER0MODRST_DMA_SET_MSK 0x00010000
> +#define ALT_RSTMGR_PER0MODRST_SPIM0_SET_MSK 0x00020000
> +#define ALT_RSTMGR_PER0MODRST_SPIM1_SET_MSK 0x00040000
> +#define ALT_RSTMGR_PER0MODRST_SPIS0_SET_MSK 0x00080000
> +#define ALT_RSTMGR_PER0MODRST_SPIS1_SET_MSK 0x00100000
> +#define ALT_RSTMGR_PER0MODRST_DMAECC_SET_MSK 0x00200000
> +#define ALT_RSTMGR_PER0MODRST_EMACPTP_SET_MSK 0x00400000
> +#define ALT_RSTMGR_PER0MODRST_DMAIF0_SET_MSK 0x01000000
> +#define ALT_RSTMGR_PER0MODRST_DMAIF1_SET_MSK 0x02000000
> +#define ALT_RSTMGR_PER0MODRST_DMAIF2_SET_MSK 0x04000000
> +#define ALT_RSTMGR_PER0MODRST_DMAIF3_SET_MSK 0x08000000
> +#define ALT_RSTMGR_PER0MODRST_DMAIF4_SET_MSK 0x10000000
> +#define ALT_RSTMGR_PER0MODRST_DMAIF5_SET_MSK 0x20000000
> +#define ALT_RSTMGR_PER0MODRST_DMAIF6_SET_MSK 0x40000000
> +#define ALT_RSTMGR_PER0MODRST_DMAIF7_SET_MSK 0x80000000
> +
> +#define ALT_RSTMGR_PER1MODRST_WD0_SET_MSK 0x00000001
> +#define ALT_RSTMGR_PER1MODRST_WD1_SET_MSK 0x00000002
> +#define ALT_RSTMGR_PER1MODRST_L4SYSTMR0_SET_MSK 0x00000004
> +#define ALT_RSTMGR_PER1MODRST_L4SYSTMR1_SET_MSK 0x00000008
> +#define ALT_RSTMGR_PER1MODRST_SPTMR0_SET_MSK 0x00000010
> +#define ALT_RSTMGR_PER1MODRST_SPTMR1_SET_MSK 0x00000020
> +#define ALT_RSTMGR_PER1MODRST_I2C0_SET_MSK 0x00000100
> +#define ALT_RSTMGR_PER1MODRST_I2C1_SET_MSK 0x00000200
> +#define ALT_RSTMGR_PER1MODRST_I2C2_SET_MSK 0x00000400
> +#define ALT_RSTMGR_PER1MODRST_I2C3_SET_MSK 0x00000800
> +#define ALT_RSTMGR_PER1MODRST_I2C4_SET_MSK 0x00001000
> +#define ALT_RSTMGR_PER1MODRST_UART0_SET_MSK 0x00010000
> +#define ALT_RSTMGR_PER1MODRST_UART1_SET_MSK 0x00020000
> +#define ALT_RSTMGR_PER1MODRST_GPIO0_SET_MSK 0x01000000
> +#define ALT_RSTMGR_PER1MODRST_GPIO1_SET_MSK 0x02000000
> +#define ALT_RSTMGR_PER1MODRST_GPIO2_SET_MSK 0x04000000
> +
> +#define ALT_RSTMGR_BRGMODRST_H2F_SET_MSK 0x00000001
> +#define ALT_RSTMGR_BRGMODRST_LWH2F_SET_MSK 0x00000002
> +#define ALT_RSTMGR_BRGMODRST_F2H_SET_MSK 0x00000004
> +#define ALT_RSTMGR_BRGMODRST_F2SSDRAM0_SET_MSK 0x00000008
> +#define ALT_RSTMGR_BRGMODRST_F2SSDRAM1_SET_MSK 0x00000010
> +#define ALT_RSTMGR_BRGMODRST_F2SSDRAM2_SET_MSK 0x00000020
> +#define ALT_RSTMGR_BRGMODRST_DDRSCH_SET_MSK 0x00000040
> +
> +#define ALT_RSTMGR_HDSKEN_SDRSELFREFEN_SET_MSK 0x00000001
> +#define ALT_RSTMGR_HDSKEN_FPGAMGRHSEN_SET_MSK 0x00000002
> +#define ALT_RSTMGR_HDSKEN_FPGAHSEN_SET_MSK 0x00000004
> +#define ALT_RSTMGR_HDSKEN_ETRSTALLEN_SET_MSK 0x00000008
> +#endif
> #endif /* _RESET_MANAGER_H_ */
> diff --git a/arch/arm/mach-socfpga/reset_manager.c b/arch/arm/mach-socfpga/reset_manager.c
> index d0ff6c4..cc370dc 100644
> --- a/arch/arm/mach-socfpga/reset_manager.c
> +++ b/arch/arm/mach-socfpga/reset_manager.c
> @@ -1,5 +1,5 @@
> /*
> - * Copyright (C) 2013 Altera Corporation <www.altera.com>
> + * Copyright (C) 2013-2016 Altera Corporation <www.altera.com>
2017 , fix globally
> * SPDX-License-Identifier: GPL-2.0+
> */
> @@ -7,71 +7,12 @@
>
> #include <common.h>
> #include <asm/io.h>
> -#include <asm/arch/fpga_manager.h>
> #include <asm/arch/reset_manager.h>
> -#include <asm/arch/system_manager.h>
>
> DECLARE_GLOBAL_DATA_PTR;
>
> static const struct socfpga_reset_manager *reset_manager_base =
> (void *)SOCFPGA_RSTMGR_ADDRESS;
> -static struct socfpga_system_manager *sysmgr_regs =
> - (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
> -
> -/*
> - * Assert or de-assert SoCFPGA reset manager reset.
> - */
> -void socfpga_per_reset(u32 reset, int set)
> -{
> - const void *reg;
> -
> - if (RSTMGR_BANK(reset) == 0)
> - reg = &reset_manager_base->mpu_mod_reset;
> - else if (RSTMGR_BANK(reset) == 1)
> - reg = &reset_manager_base->per_mod_reset;
> - else if (RSTMGR_BANK(reset) == 2)
> - reg = &reset_manager_base->per2_mod_reset;
> - else if (RSTMGR_BANK(reset) == 3)
> - reg = &reset_manager_base->brg_mod_reset;
> - else if (RSTMGR_BANK(reset) == 4)
> - reg = &reset_manager_base->misc_mod_reset;
> - else /* Invalid reset register, do nothing */
> - return;
> -
> - if (set)
> - setbits_le32(reg, 1 << RSTMGR_RESET(reset));
> - else
> - clrbits_le32(reg, 1 << RSTMGR_RESET(reset));
> -}
> -
> -/*
> - * Assert reset on every peripheral but L4WD0.
> - * Watchdog must be kept intact to prevent glitches
> - * and/or hangs.
> - * For the Arria10, we disable all the peripherals except L4 watchdog0,
> - * L4 Timer 0, and ECC.
> - */
> -void socfpga_per_reset_all(void)
> -{
> -#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> - const u32 l4wd0 = 1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0));
> -
> - writel(~l4wd0, &reset_manager_base->per_mod_reset);
> - writel(0xffffffff, &reset_manager_base->per2_mod_reset);
> -#else
> - const u32 l4wd0 = (1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0)) |
> - (1 << RSTMGR_RESET(SOCFPGA_RESET(L4SYSTIMER0))));
> -
> - unsigned mask_ecc_ocp = 0x0000FF00;
> -
> - /* disable all components except ECC_OCP, L4 Timer0 and L4 WD0 */
> - writel(~l4wd0, &reset_manager_base->per1_mod_reset);
> - setbits_le32(&reset_manager_base->per0_mod_reset, ~mask_ecc_ocp);
> -
> - /* Finally disable the ECC_OCP */
> - setbits_le32(&reset_manager_base->per0_mod_reset, mask_ecc_ocp);
> -#endif
> -}
>
> /*
> * Write the reset manager register to cause reset
> @@ -89,54 +30,3 @@ void reset_cpu(ulong addr)
> ;
> }
>
> -#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> -/*
> - * Release peripherals from reset based on handoff
> - */
> -void reset_deassert_peripherals_handoff(void)
> -{
> - writel(0, &reset_manager_base->per_mod_reset);
> -}
> -#endif
> -
> -#if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
> -void socfpga_bridges_reset(int enable)
> -{
> - /* For SoCFPGA-VT, this is NOP. */
> -}
> -#else
> -
> -#define L3REGS_REMAP_LWHPS2FPGA_MASK 0x10
> -#define L3REGS_REMAP_HPS2FPGA_MASK 0x08
> -#define L3REGS_REMAP_OCRAM_MASK 0x01
> -
> -void socfpga_bridges_reset(int enable)
> -{
> -#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
I think you added the ifdef here only to remove it again, well fix that.
> - const uint32_t l3mask = L3REGS_REMAP_LWHPS2FPGA_MASK |
> - L3REGS_REMAP_HPS2FPGA_MASK |
> - L3REGS_REMAP_OCRAM_MASK;
> -
> - if (enable) {
> - /* brdmodrst */
> - writel(0xffffffff, &reset_manager_base->brg_mod_reset);
> - } else {
> - writel(0, &sysmgr_regs->iswgrp_handoff[0]);
> - writel(l3mask, &sysmgr_regs->iswgrp_handoff[1]);
> -
> - /* Check signal from FPGA. */
> - if (!fpgamgr_test_fpga_ready()) {
> - /* FPGA not ready, do nothing. */
> - printf("%s: FPGA not ready, aborting.\n", __func__);
> - return;
> - }
> -
> - /* brdmodrst */
> - writel(0, &reset_manager_base->brg_mod_reset);
> -
> - /* Remap the bridges into memory map */
> - writel(l3mask, SOCFPGA_L3REGS_ADDRESS);
> - }
> -#endif
> -}
> -#endif
> diff --git a/arch/arm/mach-socfpga/reset_manager_arria10.c b/arch/arm/mach-socfpga/reset_manager_arria10.c
> new file mode 100644
> index 0000000..66ccebc
> --- /dev/null
> +++ b/arch/arm/mach-socfpga/reset_manager_arria10.c
> @@ -0,0 +1,407 @@
> +/*
> + * Copyright (C) 2016, Intel Corporation
> + *
> + * SPDX-License-Identifier: GPL-2.0
> + */
> +
> +#include <common.h>
> +#include <asm/io.h>
> +#include <asm/arch/fpga_manager.h>
> +#include <asm/arch/misc.h>
> +#include <asm/arch/reset_manager.h>
> +#include <asm/arch/system_manager.h>
> +#include <fdtdec.h>
> +#include <errno.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +static const struct socfpga_reset_manager *reset_manager_base =
> + (void *)SOCFPGA_RSTMGR_ADDRESS;
> +static const struct socfpga_system_manager *sysmgr_regs =
> + (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
> +
> +static int get_bridge_init_val(const void *blob, int compat_id);
> +
> +#define ECC_MASK (ALT_RSTMGR_PER0MODRST_EMACECC0_SET_MSK|\
> + ALT_RSTMGR_PER0MODRST_EMACECC1_SET_MSK|\
> + ALT_RSTMGR_PER0MODRST_EMACECC2_SET_MSK|\
> + ALT_RSTMGR_PER0MODRST_NANDECC_SET_MSK|\
> + ALT_RSTMGR_PER0MODRST_QSPIECC_SET_MSK|\
> + ALT_RSTMGR_PER0MODRST_SDMMCECC_SET_MSK)
> +
> +void reset_assert_uart(void)
> +{
> + u32 mask = 0;
> + unsigned int com_port;
> +
> + com_port = uart_com_port(gd->fdt_blob);
> +
> + if (SOCFPGA_UART1_ADDRESS == com_port)
> + mask |= ALT_RSTMGR_PER1MODRST_UART1_SET_MSK;
> + else if (SOCFPGA_UART0_ADDRESS == com_port)
> + mask |= ALT_RSTMGR_PER1MODRST_UART0_SET_MSK;
> +
> + setbits_le32(&reset_manager_base->per1modrst, mask);
> +}
> +
> +void reset_deassert_uart(void)
> +{
> + u32 mask = 0;
> + unsigned int com_port;
> +
> + com_port = uart_com_port(gd->fdt_blob);
> +
> + if (SOCFPGA_UART1_ADDRESS == com_port)
> + mask |= ALT_RSTMGR_PER1MODRST_UART1_SET_MSK;
> + else if (SOCFPGA_UART0_ADDRESS == com_port)
> + mask |= ALT_RSTMGR_PER1MODRST_UART0_SET_MSK;
> +
> + clrbits_le32(&reset_manager_base->per1modrst, mask);
> +}
> +
> +static const uint32_t per0fpgamasks[] = {
Are all these needed ? It seems like they'll only take up space for
little value.
btw use u32 all over the place
> + ALT_RSTMGR_PER0MODRST_EMACECC0_SET_MSK |
> + ALT_RSTMGR_PER0MODRST_EMAC0_SET_MSK,
> + ALT_RSTMGR_PER0MODRST_EMACECC1_SET_MSK |
> + ALT_RSTMGR_PER0MODRST_EMAC1_SET_MSK,
> + ALT_RSTMGR_PER0MODRST_EMACECC2_SET_MSK |
> + ALT_RSTMGR_PER0MODRST_EMAC2_SET_MSK,
> + 0, /* i2c0 per1mod */
> + 0, /* i2c1 per1mod */
> + 0, /* i2c0_emac */
> + 0, /* i2c1_emac */
> + 0, /* i2c2_emac */
> + ALT_RSTMGR_PER0MODRST_NANDECC_SET_MSK |
> + ALT_RSTMGR_PER0MODRST_NAND_SET_MSK,
> + ALT_RSTMGR_PER0MODRST_QSPIECC_SET_MSK |
> + ALT_RSTMGR_PER0MODRST_QSPI_SET_MSK,
> + ALT_RSTMGR_PER0MODRST_SDMMCECC_SET_MSK |
> + ALT_RSTMGR_PER0MODRST_SDMMC_SET_MSK,
> + ALT_RSTMGR_PER0MODRST_SPIM0_SET_MSK,
> + ALT_RSTMGR_PER0MODRST_SPIM1_SET_MSK,
> + ALT_RSTMGR_PER0MODRST_SPIS0_SET_MSK,
> + ALT_RSTMGR_PER0MODRST_SPIS1_SET_MSK,
> + 0, /* uart0 per1mod */
> + 0, /* uart1 per1mod */
> +};
> +
> +static const uint32_t per1fpgamasks[] = {
> + 0, /* emac0 per0mod */
> + 0, /* emac1 per0mod */
> + 0, /* emac2 per0mod */
> + ALT_RSTMGR_PER1MODRST_I2C0_SET_MSK,
> + ALT_RSTMGR_PER1MODRST_I2C1_SET_MSK,
> + ALT_RSTMGR_PER1MODRST_I2C2_SET_MSK, /* i2c0_emac */
> + ALT_RSTMGR_PER1MODRST_I2C3_SET_MSK, /* i2c1_emac */
> + ALT_RSTMGR_PER1MODRST_I2C4_SET_MSK, /* i2c2_emac */
> + 0, /* nand per0mod */
> + 0, /* qspi per0mod */
> + 0, /* sdmmc per0mod */
> + 0, /* spim0 per0mod */
> + 0, /* spim1 per0mod */
> + 0, /* spis0 per0mod */
> + 0, /* spis1 per0mod */
> + ALT_RSTMGR_PER1MODRST_UART0_SET_MSK,
> + ALT_RSTMGR_PER1MODRST_UART1_SET_MSK,
> +};
> +
> +struct bridge_cfg {
> + int compat_id;
> + u32 mask_noc;
> + u32 mask_rstmgr;
> +};
> +
> +static const struct bridge_cfg bridge_cfg_tbl[] = {
> + {
> + COMPAT_ALTERA_SOCFPGA_H2F_BRG,
> + ALT_SYSMGR_NOC_H2F_SET_MSK,
> + ALT_RSTMGR_BRGMODRST_H2F_SET_MSK,
> + },
> + {
> + COMPAT_ALTERA_SOCFPGA_LWH2F_BRG,
> + ALT_SYSMGR_NOC_LWH2F_SET_MSK,
> + ALT_RSTMGR_BRGMODRST_LWH2F_SET_MSK,
> + },
> + {
> + COMPAT_ALTERA_SOCFPGA_F2H_BRG,
> + ALT_SYSMGR_NOC_F2H_SET_MSK,
> + ALT_RSTMGR_BRGMODRST_F2H_SET_MSK,
> + },
> + {
> + COMPAT_ALTERA_SOCFPGA_F2SDR0,
> + ALT_SYSMGR_NOC_F2SDR0_SET_MSK,
> + ALT_RSTMGR_BRGMODRST_F2SSDRAM0_SET_MSK,
> + },
> + {
> + COMPAT_ALTERA_SOCFPGA_F2SDR1,
> + ALT_SYSMGR_NOC_F2SDR1_SET_MSK,
> + ALT_RSTMGR_BRGMODRST_F2SSDRAM1_SET_MSK,
> + },
> + {
> + COMPAT_ALTERA_SOCFPGA_F2SDR2,
> + ALT_SYSMGR_NOC_F2SDR2_SET_MSK,
> + ALT_RSTMGR_BRGMODRST_F2SSDRAM2_SET_MSK,
> + },
> +};
> +
> +/* Disable the watchdog (toggle reset to watchdog) */
> +void watchdog_disable(void)
> +{
> + /* assert reset for watchdog */
> + setbits_le32(&reset_manager_base->per1modrst,
> + ALT_RSTMGR_PER1MODRST_WD0_SET_MSK);
> +
> +}
> +
> +/* Release NOC ddr scheduler from reset */
> +void reset_deassert_noc_ddr_scheduler(void)
> +{
> + clrbits_le32(&reset_manager_base->brgmodrst,
> + ALT_RSTMGR_BRGMODRST_DDRSCH_SET_MSK);
> +}
> +
> +/* Check whether Watchdog in reset state? */
> +int is_wdt_in_reset(void)
> +{
> + unsigned long val;
u32
> + val = readl(&reset_manager_base->per1modrst);
> + val &= ALT_RSTMGR_PER1MODRST_WD0_SET_MSK;
> +
> + /* return 0x1 if watchdog in reset */
> + return val;
> +}
> +
> +/* emacbase: base address of emac to enable/disable reset
> + * state: 0 - disable reset, !0 - enable reset
> + */
> +void emac_manage_reset(ulong emacbase, uint state)
> +{
> + ulong eccmask;
> + ulong emacmask;
> + switch (emacbase) {
> + case SOCFPGA_EMAC0_ADDRESS:
> + eccmask = ALT_RSTMGR_PER0MODRST_EMACECC0_SET_MSK;
> + emacmask = ALT_RSTMGR_PER0MODRST_EMAC0_SET_MSK;
> + break;
> + case SOCFPGA_EMAC1_ADDRESS:
> + eccmask = ALT_RSTMGR_PER0MODRST_EMACECC1_SET_MSK;
> + emacmask = ALT_RSTMGR_PER0MODRST_EMAC1_SET_MSK;
> + break;
> + case SOCFPGA_EMAC2_ADDRESS:
> + eccmask = ALT_RSTMGR_PER0MODRST_EMACECC2_SET_MSK;
> + emacmask = ALT_RSTMGR_PER0MODRST_EMAC2_SET_MSK;
> + break;
> + default:
> + error("emac base address unexpected! %lx", emacbase);
> + hang();
> + break;
> + }
> +
> + if (state) {
> + /* Enable ECC OCP first */
> + setbits_le32(&reset_manager_base->per0modrst, eccmask);
> + setbits_le32(&reset_manager_base->per0modrst, emacmask);
> + } else {
> + /* Disable ECC OCP first */
> + clrbits_le32(&reset_manager_base->per0modrst, emacmask);
> + clrbits_le32(&reset_manager_base->per0modrst, eccmask);
> + }
> +}
> +
> +static int get_bridge_init_val(const void *blob, int compat_id)
> +{
> + int rval = 0;
> + int node;
> + u32 val;
> +
> + node = fdtdec_next_compatible(blob, 0, compat_id);
> + if (node >= 0) {
> + if (!fdtdec_get_int_array(blob, node, "init-val", &val, 1)) {
> + if (val == 1)
> + rval = val;
> + }
> + }
> + return rval;
> +}
> +
> +/* Enable bridges (hps2fpga, lwhps2fpga, fpga2hps, fpga2sdram) per handoff */
> +int reset_deassert_bridges_handoff(void)
> +{
> + u32 mask_noc = 0, mask_rstmgr = 0;
> + int i;
> + unsigned start = get_timer(0);
> +
> + for (i = 0; i < ARRAY_SIZE(bridge_cfg_tbl); i++) {
> + if (get_bridge_init_val(gd->fdt_blob,
> + bridge_cfg_tbl[i].compat_id)) {
> + mask_noc |= bridge_cfg_tbl[i].mask_noc;
> + mask_rstmgr |= bridge_cfg_tbl[i].mask_rstmgr;
> + }
> + }
> +
> + /* clear idle request to all bridges */
> + setbits_le32(&sysmgr_regs->noc_idlereq_clr, mask_noc);
> +
> + /* Release bridges from reset state per handoff value */
> + clrbits_le32(&reset_manager_base->brgmodrst, mask_rstmgr);
> +
> + /* Poll until all idleack to 0, timeout at 1000ms */
> + while (readl(&sysmgr_regs->noc_idleack) & mask_noc) {
> + if (get_timer(start) > 1000) {
> + printf("Fail: noc_idleack = 0x%08x mask_noc = 0x%08x\n",
> + readl(&sysmgr_regs->noc_idleack),
> + mask_noc);
> + return -ETIMEDOUT;
> + }
> + }
> + return 0;
> +}
> +
> +void reset_assert_fpga_connected_peripherals(void)
> +{
> + uint32_t mask0 = 0;
> + uint32_t mask1 = 0;
> + uint32_t fpga_pinux_addr = SOCFPGA_PINMUX_FPGA_INTERFACE_ADDRESS;
> + int i;
> +
> + for (i = 0; i < ARRAY_SIZE(per1fpgamasks); i++) {
> + if (readl(fpga_pinux_addr)) {
> + mask0 |= per0fpgamasks[i];
> + mask1 |= per1fpgamasks[i];
> + }
> + fpga_pinux_addr += sizeof(uint32_t);
> + }
> +
> + setbits_le32(&reset_manager_base->per0modrst, mask0 & ECC_MASK);
> + setbits_le32(&reset_manager_base->per1modrst, mask1);
> + setbits_le32(&reset_manager_base->per0modrst, mask0);
> +}
> +
> +/* Release L4 OSC1 Watchdog Timer 0 from reset through reset manager */
> +void reset_deassert_osc1wd0(void)
> +{
> + clrbits_le32(&reset_manager_base->per1modrst,
> + ALT_RSTMGR_PER1MODRST_WD0_SET_MSK);
> +}
> +
> +/*
> + * Assert or de-assert SoCFPGA reset manager reset.
> + */
> +void socfpga_per_reset(u32 reset, int set)
> +{
> + const volatile uint32_t *reg;
> + uint32_t rstmgr_bank = RSTMGR_BANK(reset);
> +
> + switch (rstmgr_bank) {
> + case 0:
> + reg = &reset_manager_base->mpumodrst;
> + break;
> + case 1:
> + reg = &reset_manager_base->per0modrst;
> + break;
> + case 2:
> + reg = &reset_manager_base->per1modrst;
> + break;
> + case 3:
> + reg = &reset_manager_base->brgmodrst;
> + break;
> + case 4:
> + reg = &reset_manager_base->sysmodrst;
> + break;
> +
> + default:
> + return;
> + }
> +
> + if (set)
> + setbits_le32(reg, 1 << RSTMGR_RESET(reset));
> + else
> + clrbits_le32(reg, 1 << RSTMGR_RESET(reset));
> +}
> +
> +/*
> + * Assert reset on every peripheral but L4WD0.
> + * Watchdog must be kept intact to prevent glitches
> + * and/or hangs.
> + * For the Arria10, we disable all the peripherals except L4 watchdog0,
> + * L4 Timer 0, and ECC.
> + */
> +void socfpga_per_reset_all(void)
> +{
> + const u32 l4wd0 = (1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0)) |
> + (1 << RSTMGR_RESET(SOCFPGA_RESET(L4SYSTIMER0))));
> +
> + unsigned mask_ecc_ocp =
> + ALT_RSTMGR_PER0MODRST_EMACECC0_SET_MSK |
> + ALT_RSTMGR_PER0MODRST_EMACECC1_SET_MSK |
> + ALT_RSTMGR_PER0MODRST_EMACECC2_SET_MSK |
> + ALT_RSTMGR_PER0MODRST_USBECC0_SET_MSK |
> + ALT_RSTMGR_PER0MODRST_USBECC1_SET_MSK |
> + ALT_RSTMGR_PER0MODRST_NANDECC_SET_MSK |
> + ALT_RSTMGR_PER0MODRST_QSPIECC_SET_MSK |
> + ALT_RSTMGR_PER0MODRST_SDMMCECC_SET_MSK;
> +
> + /* disable all components except ECC_OCP, L4 Timer0 and L4 WD0 */
> + writel(~l4wd0, &reset_manager_base->per1modrst);
> + setbits_le32(&reset_manager_base->per0modrst, ~mask_ecc_ocp);
> +
> + /* Finally disable the ECC_OCP */
> + setbits_le32(&reset_manager_base->per0modrst, mask_ecc_ocp);
> +}
> +
> +#if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
> +void socfpga_bridges_reset(int enable)
> +{
> + /* For SoCFPGA-VT, this is NOP. */
VT is a thing on Arria 10 ?
> +}
> +#else
> +void socfpga_bridges_reset(int enable)
> +{
> +/* Disable all the bridges (hps2fpga, lwhps2fpga, fpga2hps, fpga2sdram) */
> + /* set idle request to all bridges */
> + writel(ALT_SYSMGR_NOC_H2F_SET_MSK |
> + ALT_SYSMGR_NOC_LWH2F_SET_MSK |
> + ALT_SYSMGR_NOC_F2H_SET_MSK |
> + ALT_SYSMGR_NOC_F2SDR0_SET_MSK |
> + ALT_SYSMGR_NOC_F2SDR1_SET_MSK |
> + ALT_SYSMGR_NOC_F2SDR2_SET_MSK,
> + &sysmgr_regs->noc_idlereq_set);
> +
> + /* Enable the NOC timeout */
> + writel(ALT_SYSMGR_NOC_TMO_EN_SET_MSK,
> + &sysmgr_regs->noc_timeout);
> +
> + /* Poll until all idleack to 1 */
> + while ((readl(&sysmgr_regs->noc_idleack) ^
> + (ALT_SYSMGR_NOC_H2F_SET_MSK |
> + ALT_SYSMGR_NOC_LWH2F_SET_MSK |
> + ALT_SYSMGR_NOC_F2H_SET_MSK |
> + ALT_SYSMGR_NOC_F2SDR0_SET_MSK |
> + ALT_SYSMGR_NOC_F2SDR1_SET_MSK |
> + ALT_SYSMGR_NOC_F2SDR2_SET_MSK)))
> + ;
> +
> + /* Poll until all idlestatus to 1 */
> + while ((readl(&sysmgr_regs->noc_idlestatus) ^
> + (ALT_SYSMGR_NOC_H2F_SET_MSK |
> + ALT_SYSMGR_NOC_LWH2F_SET_MSK |
> + ALT_SYSMGR_NOC_F2H_SET_MSK |
> + ALT_SYSMGR_NOC_F2SDR0_SET_MSK |
> + ALT_SYSMGR_NOC_F2SDR1_SET_MSK |
> + ALT_SYSMGR_NOC_F2SDR2_SET_MSK)))
> + ;
> +
> + /* Put all bridges (except NOR DDR scheduler) into reset state */
> + setbits_le32(&reset_manager_base->brgmodrst,
> + (ALT_RSTMGR_BRGMODRST_H2F_SET_MSK |
> + ALT_RSTMGR_BRGMODRST_LWH2F_SET_MSK |
> + ALT_RSTMGR_BRGMODRST_F2H_SET_MSK |
> + ALT_RSTMGR_BRGMODRST_F2SSDRAM0_SET_MSK |
> + ALT_RSTMGR_BRGMODRST_F2SSDRAM1_SET_MSK |
> + ALT_RSTMGR_BRGMODRST_F2SSDRAM2_SET_MSK));
> +
> + /* Disable NOC timeout */
> + writel(0, &sysmgr_regs->noc_timeout);
> +}
> +#endif
> diff --git a/arch/arm/mach-socfpga/reset_manager.c b/arch/arm/mach-socfpga/reset_manager_gen5.c
> similarity index 58%
> copy from arch/arm/mach-socfpga/reset_manager.c
> copy to arch/arm/mach-socfpga/reset_manager_gen5.c
> index d0ff6c4..8c1f96e 100644
> --- a/arch/arm/mach-socfpga/reset_manager.c
> +++ b/arch/arm/mach-socfpga/reset_manager_gen5.c
> @@ -1,10 +1,9 @@
> /*
> - * Copyright (C) 2013 Altera Corporation <www.altera.com>
> + * Copyright (C) 2016, Intel Corporation
> *
> - * SPDX-License-Identifier: GPL-2.0+
> + * SPDX-License-Identifier: GPL-2.0
Oh really ? Did you get approval from every single contributor to change
license of this file ? Sorry, I disagree with this change,
so remove this.
> */
>
> -
> #include <common.h>
> #include <asm/io.h>
> #include <asm/arch/fpga_manager.h>
> @@ -15,28 +14,45 @@ DECLARE_GLOBAL_DATA_PTR;
>
> static const struct socfpga_reset_manager *reset_manager_base =
> (void *)SOCFPGA_RSTMGR_ADDRESS;
> -static struct socfpga_system_manager *sysmgr_regs =
> +static const struct socfpga_system_manager *sysmgr_regs =
> (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
>
> /*
> + * Release peripherals from reset based on handoff
> + */
> +void reset_deassert_peripherals_handoff(void)
> +{
> + writel(0, &reset_manager_base->per_mod_reset);
> +}
> +
> +/*
> * Assert or de-assert SoCFPGA reset manager reset.
> */
> void socfpga_per_reset(u32 reset, int set)
> {
> - const void *reg;
> -
> - if (RSTMGR_BANK(reset) == 0)
> - reg = &reset_manager_base->mpu_mod_reset;
> - else if (RSTMGR_BANK(reset) == 1)
> - reg = &reset_manager_base->per_mod_reset;
> - else if (RSTMGR_BANK(reset) == 2)
> - reg = &reset_manager_base->per2_mod_reset;
> - else if (RSTMGR_BANK(reset) == 3)
> - reg = &reset_manager_base->brg_mod_reset;
> - else if (RSTMGR_BANK(reset) == 4)
> - reg = &reset_manager_base->misc_mod_reset;
> - else /* Invalid reset register, do nothing */
> - return;
> + const volatile uint32_t *reg;
> + uint32_t rstmgr_bank = RSTMGR_BANK(reset);
> +
> + switch (rstmgr_bank) {
> + case 0:
How is this change relevant to this patch ? Seems completely unrelated,
so drop this.
> + reg = &reset_manager_base->mpu_mod_reset;
> + break;
> + case 1:
> + reg = &reset_manager_base->per_mod_reset;
> + break;
> + case 2:
> + reg = &reset_manager_base->per2_mod_reset;
> + break;
> + case 3:
> + reg = &reset_manager_base->brg_mod_reset;
> + break;
> + case 4:
> + reg = &reset_manager_base->misc_mod_reset;
> + break;
> +
> + default:
> + return;
> + }
>
> if (set)
> setbits_le32(reg, 1 << RSTMGR_RESET(reset));
> @@ -53,52 +69,12 @@ void socfpga_per_reset(u32 reset, int set)
> */
> void socfpga_per_reset_all(void)
> {
> -#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> const u32 l4wd0 = 1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0));
>
> writel(~l4wd0, &reset_manager_base->per_mod_reset);
> writel(0xffffffff, &reset_manager_base->per2_mod_reset);
> -#else
> - const u32 l4wd0 = (1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0)) |
> - (1 << RSTMGR_RESET(SOCFPGA_RESET(L4SYSTIMER0))));
> -
> - unsigned mask_ecc_ocp = 0x0000FF00;
> -
> - /* disable all components except ECC_OCP, L4 Timer0 and L4 WD0 */
> - writel(~l4wd0, &reset_manager_base->per1_mod_reset);
> - setbits_le32(&reset_manager_base->per0_mod_reset, ~mask_ecc_ocp);
> -
> - /* Finally disable the ECC_OCP */
> - setbits_le32(&reset_manager_base->per0_mod_reset, mask_ecc_ocp);
> -#endif
> }
>
> -/*
> - * Write the reset manager register to cause reset
> - */
> -void reset_cpu(ulong addr)
> -{
> - /* request a warm reset */
> - writel((1 << RSTMGR_CTRL_SWWARMRSTREQ_LSB),
Drop parenthesis around 1 << n .
> - &reset_manager_base->ctrl);
> - /*
> - * infinite loop here as watchdog will trigger and reset
> - * the processor
> - */
> - while (1)
> - ;
> -}
> -
> -#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> -/*
> - * Release peripherals from reset based on handoff
> - */
> -void reset_deassert_peripherals_handoff(void)
> -{
> - writel(0, &reset_manager_base->per_mod_reset);
> -}
> -#endif
> -
> #if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
> void socfpga_bridges_reset(int enable)
> {
> @@ -112,7 +88,6 @@ void socfpga_bridges_reset(int enable)
>
> void socfpga_bridges_reset(int enable)
> {
> -#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> const uint32_t l3mask = L3REGS_REMAP_LWHPS2FPGA_MASK |
> L3REGS_REMAP_HPS2FPGA_MASK |
> L3REGS_REMAP_OCRAM_MASK;
> @@ -137,6 +112,5 @@ void socfpga_bridges_reset(int enable)
> /* Remap the bridges into memory map */
> writel(l3mask, SOCFPGA_L3REGS_ADDRESS);
> }
> -#endif
> }
> #endif
>
--
Best regards,
Marek Vasut
More information about the U-Boot
mailing list