[U-Boot] [UBOOT v2 09/15] mmc: sdhci: zynqmp: Add support of SD3.0
Siva Durga Prasad Paladugu
siva.durga.paladugu at xilinx.com
Mon Jan 30 11:38:26 CET 2017
Add SD3.0 support for ZynqMP, this support needs a
platform specific tuning and tap delays for UHS
modes of SD3.0 and this patch takes care of it.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur at xilinx.com>
---
Changes from v1:
- None
---
board/xilinx/zynqmp/Makefile | 1 +
board/xilinx/zynqmp/tap_delays.c | 249 +++++++++++++++++++++++++++++++++++++++
drivers/mmc/zynq_sdhci.c | 142 +++++++++++++++++++++-
include/zynqmp_tap_delay.h | 20 ++++
4 files changed, 411 insertions(+), 1 deletion(-)
create mode 100644 board/xilinx/zynqmp/tap_delays.c
create mode 100644 include/zynqmp_tap_delay.h
diff --git a/board/xilinx/zynqmp/Makefile b/board/xilinx/zynqmp/Makefile
index 9d69d65..2bf0375 100644
--- a/board/xilinx/zynqmp/Makefile
+++ b/board/xilinx/zynqmp/Makefile
@@ -20,6 +20,7 @@ $(warning Put custom psu_init_gpl.c/h to board/xilinx/zynqmp/custom_hw_platform/
endif
endif
+obj-$(CONFIG_ZYNQ_SDHCI) += tap_delays.o
obj-$(CONFIG_SPL_BUILD) += $(init-objs)
# Suppress "warning: function declaration isn't a prototype"
diff --git a/board/xilinx/zynqmp/tap_delays.c b/board/xilinx/zynqmp/tap_delays.c
new file mode 100644
index 0000000..d57587e
--- /dev/null
+++ b/board/xilinx/zynqmp/tap_delays.c
@@ -0,0 +1,249 @@
+/*
+ * Xilinx ZynqMP SoC Tap Delay Programming
+ *
+ * Copyright (C) 2016 Xilinx, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+
+#define SD_DLL_CTRL 0xFF180358
+#define SD_ITAP_DLY 0xFF180314
+#define SD_OTAP_DLY 0xFF180318
+#define SD0_DLL_RST_MASK 0x00000004
+#define SD0_DLL_RST 0x00000004
+#define SD1_DLL_RST_MASK 0x00040000
+#define SD1_DLL_RST 0x00040000
+#define SD0_ITAPCHGWIN_MASK 0x00000200
+#define SD0_ITAPCHGWIN 0x00000200
+#define SD1_ITAPCHGWIN_MASK 0x02000000
+#define SD1_ITAPCHGWIN 0x02000000
+#define SD0_ITAPDLYENA_MASK 0x00000100
+#define SD0_ITAPDLYENA 0x00000100
+#define SD1_ITAPDLYENA_MASK 0x01000000
+#define SD1_ITAPDLYENA 0x01000000
+#define SD0_ITAPDLYSEL_MASK 0x000000FF
+#define SD0_ITAPDLYSEL_HSD 0x00000015
+#define SD0_ITAPDLYSEL_SD_DDR50 0x0000003D
+#define SD0_ITAPDLYSEL_MMC_DDR50 0x00000012
+
+#define SD1_ITAPDLYSEL_MASK 0x00FF0000
+#define SD1_ITAPDLYSEL_HSD 0x00150000
+#define SD1_ITAPDLYSEL_SD_DDR50 0x003D0000
+#define SD1_ITAPDLYSEL_MMC_DDR50 0x00120000
+
+#define SD0_OTAPDLYENA_MASK 0x00000040
+#define SD0_OTAPDLYENA 0x00000040
+#define SD1_OTAPDLYENA_MASK 0x00400000
+#define SD1_OTAPDLYENA 0x00400000
+#define SD0_OTAPDLYSEL_MASK 0x0000003F
+#define SD0_OTAPDLYSEL_MMC_HSD 0x00000006
+#define SD0_OTAPDLYSEL_SD_HSD 0x00000005
+#define SD0_OTAPDLYSEL_SDR50 0x00000003
+#define SD0_OTAPDLYSEL_SDR104_B0 0x00000003
+#define SD0_OTAPDLYSEL_SDR104_B2 0x00000002
+#define SD0_OTAPDLYSEL_SD_DDR50 0x00000004
+#define SD0_OTAPDLYSEL_MMC_DDR50 0x00000006
+
+#define SD1_OTAPDLYSEL_MASK 0x003F0000
+#define SD1_OTAPDLYSEL_MMC_HSD 0x00060000
+#define SD1_OTAPDLYSEL_SD_HSD 0x00050000
+#define SD1_OTAPDLYSEL_SDR50 0x00030000
+#define SD1_OTAPDLYSEL_SDR104_B0 0x00030000
+#define SD1_OTAPDLYSEL_SDR104_B2 0x00020000
+#define SD1_OTAPDLYSEL_SD_DDR50 0x00040000
+#define SD1_OTAPDLYSEL_MMC_DDR50 0x00060000
+
+#define MMC_BANK2 0x2
+
+#define MMC_TIMING_UHS_SDR25 1
+#define MMC_TIMING_UHS_SDR50 2
+#define MMC_TIMING_UHS_SDR104 3
+#define MMC_TIMING_UHS_DDR50 4
+#define MMC_TIMING_MMC_HS200 5
+#define MMC_TIMING_SD_HS 6
+#define MMC_TIMING_MMC_DDR52 7
+#define MMC_TIMING_MMC_HS 8
+
+void zynqmp_dll_reset(u8 deviceid)
+{
+ /* Issue DLL Reset */
+ if (deviceid == 0)
+ zynqmp_mmio_write(SD_DLL_CTRL, SD0_DLL_RST_MASK,
+ SD0_DLL_RST);
+ else
+ zynqmp_mmio_write(SD_DLL_CTRL, SD1_DLL_RST_MASK,
+ SD1_DLL_RST);
+
+ mdelay(1);
+
+ /* Release DLL Reset */
+ if (deviceid == 0)
+ zynqmp_mmio_write(SD_DLL_CTRL, SD0_DLL_RST_MASK, 0x0);
+ else
+ zynqmp_mmio_write(SD_DLL_CTRL, SD1_DLL_RST_MASK, 0x0);
+}
+
+static void arasan_zynqmp_tap_sdr104(u8 deviceid, u8 timing, u8 bank)
+{
+ if (deviceid == 0) {
+ /* Program OTAP */
+ zynqmp_mmio_write(SD_OTAP_DLY, SD0_OTAPDLYENA_MASK,
+ SD0_OTAPDLYENA);
+ if (bank == MMC_BANK2)
+ zynqmp_mmio_write(SD_OTAP_DLY, SD0_OTAPDLYSEL_MASK,
+ SD0_OTAPDLYSEL_SDR104_B2);
+ else
+ zynqmp_mmio_write(SD_OTAP_DLY, SD0_OTAPDLYSEL_MASK,
+ SD0_OTAPDLYSEL_SDR104_B0);
+ } else {
+ /* Program OTAP */
+ zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYENA_MASK,
+ SD1_OTAPDLYENA);
+ if (bank == MMC_BANK2)
+ zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK,
+ SD1_OTAPDLYSEL_SDR104_B2);
+ else
+ zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK,
+ SD1_OTAPDLYSEL_SDR104_B0);
+ }
+}
+
+static void arasan_zynqmp_tap_hs(u8 deviceid, u8 timing, u8 bank)
+{
+ if (deviceid == 0) {
+ /* Program ITAP */
+ zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPCHGWIN_MASK,
+ SD0_ITAPCHGWIN);
+ zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPDLYENA_MASK,
+ SD0_ITAPDLYENA);
+ zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPDLYSEL_MASK,
+ SD0_ITAPDLYSEL_HSD);
+ zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPCHGWIN_MASK, 0x0);
+ /* Program OTAP */
+ zynqmp_mmio_write(SD_OTAP_DLY, SD0_OTAPDLYENA_MASK,
+ SD0_OTAPDLYENA);
+ if (timing == MMC_TIMING_MMC_HS)
+ zynqmp_mmio_write(SD_OTAP_DLY, SD0_OTAPDLYSEL_MASK,
+ SD0_OTAPDLYSEL_MMC_HSD);
+ else
+ zynqmp_mmio_write(SD_OTAP_DLY, SD0_OTAPDLYSEL_MASK,
+ SD0_OTAPDLYSEL_SD_HSD);
+ } else {
+ /* Program ITAP */
+ zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPCHGWIN_MASK,
+ SD1_ITAPCHGWIN);
+ zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPDLYENA_MASK,
+ SD1_ITAPDLYENA);
+ zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPDLYSEL_MASK,
+ SD1_ITAPDLYSEL_HSD);
+ zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPCHGWIN_MASK, 0x0);
+ /* Program OTAP */
+ zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYENA_MASK,
+ SD1_OTAPDLYENA);
+ if (timing == MMC_TIMING_MMC_HS)
+ zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK,
+ SD1_OTAPDLYSEL_MMC_HSD);
+ else
+ zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK,
+ SD1_OTAPDLYSEL_SD_HSD);
+ }
+}
+
+static void arasan_zynqmp_tap_ddr50(u8 deviceid, u8 timing, u8 bank)
+{
+ if (deviceid == 0) {
+ /* Program ITAP */
+ zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPCHGWIN_MASK,
+ SD0_ITAPCHGWIN);
+ zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPDLYENA_MASK,
+ SD0_ITAPDLYENA);
+ if (timing == MMC_TIMING_UHS_DDR50)
+ zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPDLYSEL_MASK,
+ SD0_ITAPDLYSEL_SD_DDR50);
+ else
+ zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPDLYSEL_MASK,
+ SD0_ITAPDLYSEL_MMC_DDR50);
+ zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPCHGWIN_MASK, 0x0);
+ /* Program OTAP */
+ zynqmp_mmio_write(SD_OTAP_DLY, SD0_OTAPDLYENA_MASK,
+ SD0_OTAPDLYENA);
+ if (timing == MMC_TIMING_UHS_DDR50)
+ zynqmp_mmio_write(SD_OTAP_DLY, SD0_OTAPDLYSEL_MASK,
+ SD0_OTAPDLYSEL_SD_DDR50);
+ else
+ zynqmp_mmio_write(SD_OTAP_DLY, SD0_OTAPDLYSEL_MASK,
+ SD0_OTAPDLYSEL_MMC_DDR50);
+ } else {
+ /* Program ITAP */
+ zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPCHGWIN_MASK,
+ SD1_ITAPCHGWIN);
+ zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPDLYENA_MASK,
+ SD1_ITAPDLYENA);
+ if (timing == MMC_TIMING_UHS_DDR50)
+ zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPDLYSEL_MASK,
+ SD1_ITAPDLYSEL_SD_DDR50);
+ else
+ zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPDLYSEL_MASK,
+ SD1_ITAPDLYSEL_MMC_DDR50);
+ zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPCHGWIN_MASK, 0x0);
+ /* Program OTAP */
+ zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYENA_MASK,
+ SD1_OTAPDLYENA);
+ if (timing == MMC_TIMING_UHS_DDR50)
+ zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK,
+ SD1_OTAPDLYSEL_SD_DDR50);
+ else
+ zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK,
+ SD1_OTAPDLYSEL_MMC_DDR50);
+ }
+}
+
+static void arasan_zynqmp_tap_sdr50(u8 deviceid, u8 timing, u8 bank)
+{
+ if (deviceid == 0) {
+ /* Program OTAP */
+ zynqmp_mmio_write(SD_OTAP_DLY, SD0_OTAPDLYENA_MASK,
+ SD0_OTAPDLYENA);
+ zynqmp_mmio_write(SD_OTAP_DLY, SD0_OTAPDLYSEL_MASK,
+ SD0_OTAPDLYSEL_SDR50);
+ } else {
+ /* Program OTAP */
+ zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYENA_MASK,
+ SD1_OTAPDLYENA);
+ zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK,
+ SD1_OTAPDLYSEL_SDR50);
+ }
+}
+
+void arasan_zynqmp_set_tapdelay(u8 deviceid, u8 timing, u8 bank)
+{
+ if (deviceid == 0)
+ zynqmp_mmio_write(SD_DLL_CTRL, SD0_DLL_RST_MASK,
+ SD0_DLL_RST);
+ else
+ zynqmp_mmio_write(SD_DLL_CTRL, SD1_DLL_RST_MASK,
+ SD1_DLL_RST);
+
+ switch (timing) {
+ case MMC_TIMING_UHS_SDR25:
+ arasan_zynqmp_tap_hs(deviceid, timing, bank);
+ break;
+ case MMC_TIMING_UHS_SDR50:
+ arasan_zynqmp_tap_sdr50(deviceid, timing, bank);
+ break;
+ case MMC_TIMING_UHS_SDR104:
+ arasan_zynqmp_tap_sdr104(deviceid, timing, bank);
+ break;
+ case MMC_TIMING_UHS_DDR50:
+ arasan_zynqmp_tap_ddr50(deviceid, timing, bank);
+ break;
+ }
+
+ if (deviceid == 0)
+ zynqmp_mmio_write(SD_DLL_CTRL, SD0_DLL_RST_MASK, 0x0);
+ else
+ zynqmp_mmio_write(SD_DLL_CTRL, SD1_DLL_RST_MASK, 0x0);
+}
diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c
index f98089e..7c42a78 100644
--- a/drivers/mmc/zynq_sdhci.c
+++ b/drivers/mmc/zynq_sdhci.c
@@ -12,11 +12,18 @@
#include <libfdt.h>
#include <malloc.h>
#include <sdhci.h>
+#include <mmc.h>
+#include <asm/arch/hardware.h>
+#include <asm/io.h>
+#include <zynqmp_tap_delay.h>
+#include "mmc_private.h"
#ifndef CONFIG_ZYNQ_SDHCI_MIN_FREQ
# define CONFIG_ZYNQ_SDHCI_MIN_FREQ 0
#endif
+DECLARE_GLOBAL_DATA_PTR;
+
struct arasan_sdhci_plat {
struct mmc_config cfg;
struct mmc mmc;
@@ -24,8 +31,131 @@ struct arasan_sdhci_plat {
struct arasan_sdhci_priv {
struct sdhci_host *host;
+ u8 deviceid;
+ u8 bank;
};
+#if defined(CONFIG_ARCH_ZYNQMP)
+static void arasan_zynqmp_dll_reset(struct sdhci_host *host, u8 deviceid)
+{
+ u16 clk;
+ unsigned long timeout;
+
+ clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
+ clk &= ~(SDHCI_CLOCK_CARD_EN);
+ sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
+
+ /* Issue DLL Reset */
+ zynqmp_dll_reset(deviceid);
+
+ /* Wait max 20 ms */
+ timeout = 100;
+ while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
+ & SDHCI_CLOCK_INT_STABLE)) {
+ if (timeout == 0) {
+ dev_err(mmc_dev(host->mmc),
+ ": Internal clock never stabilised.\n");
+ return;
+ }
+ timeout--;
+ udelay(1000);
+ }
+
+ clk |= SDHCI_CLOCK_CARD_EN;
+ sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
+}
+
+static int arasan_sdhci_execute_tuning(struct mmc *mmc, u8 opcode)
+{
+ struct mmc_cmd cmd;
+ struct mmc_data data;
+ u32 ctrl;
+ struct sdhci_host *host;
+ struct arasan_sdhci_priv *priv = dev_get_priv(mmc->dev);
+ u8 tuning_loop_counter = 40;
+ u8 deviceid;
+
+ debug("%s\n", __func__);
+
+ host = priv->host;
+ deviceid = priv->deviceid;
+
+ ctrl = sdhci_readw(host, SDHCI_HOST_CTRL2);
+ ctrl |= SDHCI_CTRL_EXEC_TUNING;
+ sdhci_writew(host, ctrl, SDHCI_HOST_CTRL2);
+
+ mdelay(1);
+
+ arasan_zynqmp_dll_reset(host, deviceid);
+
+ sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
+ sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
+
+ do {
+ cmd.cmdidx = opcode;
+ cmd.resp_type = MMC_RSP_R1;
+ cmd.cmdarg = 0;
+
+ data.blocksize = 64;
+ data.blocks = 1;
+ data.flags = MMC_DATA_READ;
+
+ if (tuning_loop_counter-- == 0)
+ break;
+
+ if (cmd.cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200 &&
+ mmc->bus_width == 8)
+ data.blocksize = 128;
+
+ sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
+ data.blocksize),
+ SDHCI_BLOCK_SIZE);
+ sdhci_writew(host, data.blocks, SDHCI_BLOCK_COUNT);
+ sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
+
+ mmc_send_cmd(mmc, &cmd, NULL);
+ ctrl = sdhci_readw(host, SDHCI_HOST_CTRL2);
+
+ if (cmd.cmdidx == MMC_CMD_SEND_TUNING_BLOCK)
+ udelay(1);
+
+ } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
+
+ if (tuning_loop_counter < 0) {
+ ctrl &= ~SDHCI_CTRL_TUNED_CLK;
+ sdhci_writel(host, ctrl, SDHCI_HOST_CTRL2);
+ }
+
+ if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
+ debug("%s:Tuning failed\n", __func__);
+ return -1;
+ } else {
+ udelay(1);
+ arasan_zynqmp_dll_reset(host, deviceid);
+ }
+
+ /* Enable only interrupts served by the SD controller */
+ sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
+ SDHCI_INT_ENABLE);
+ /* Mask all sdhci interrupt sources */
+ sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
+
+ return 0;
+}
+
+static void arasan_sdhci_set_tapdelay(struct sdhci_host *host, u8 uhsmode)
+{
+ struct arasan_sdhci_priv *priv = dev_get_priv(host->mmc->dev);
+
+ debug("%s, %d:%d, mode:%d\n", __func__, priv->deviceid, priv->bank,
+ uhsmode);
+ if ((uhsmode >= MMC_TIMING_UHS_SDR25) &&
+ (uhsmode <= MMC_TIMING_UHS_DDR50))
+ arasan_zynqmp_set_tapdelay(priv->deviceid, uhsmode,
+ priv->bank);
+}
+#endif
+
static int arasan_sdhci_probe(struct udevice *dev)
{
struct arasan_sdhci_plat *plat = dev_get_platdata(dev);
@@ -54,6 +184,11 @@ static int arasan_sdhci_probe(struct udevice *dev)
host->mmc->dev = dev;
upriv->mmc = host->mmc;
+#if defined(CONFIG_ARCH_ZYNQMP)
+ host->ops->set_delay = arasan_sdhci_set_tapdelay;
+ host->ops->platform_execute_tuning = arasan_sdhci_execute_tuning;
+#endif
+
return sdhci_probe(dev);
}
@@ -68,6 +203,11 @@ static int arasan_sdhci_ofdata_to_platdata(struct udevice *dev)
priv->host->name = dev->name;
priv->host->ioaddr = (void *)dev_get_addr(dev);
+ priv->deviceid = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ "xlnx,device_id", -1);
+ priv->bank = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ "xlnx,mio_bank", -1);
+
return 0;
}
@@ -91,6 +231,6 @@ U_BOOT_DRIVER(arasan_sdhci_drv) = {
.ops = &sdhci_ops,
.bind = arasan_sdhci_bind,
.probe = arasan_sdhci_probe,
- .priv_auto_alloc_size = sizeof(struct sdhci_host),
+ .priv_auto_alloc_size = sizeof(struct arasan_sdhci_priv),
.platdata_auto_alloc_size = sizeof(struct arasan_sdhci_plat),
};
diff --git a/include/zynqmp_tap_delay.h b/include/zynqmp_tap_delay.h
new file mode 100644
index 0000000..14cff9d
--- /dev/null
+++ b/include/zynqmp_tap_delay.h
@@ -0,0 +1,20 @@
+/*
+ * Xilinx ZynqMP SoC Tap Delay Programming
+ *
+ * Copyright (C) 2016 Xilinx, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ZYNQMP_TAP_DELAY_H__
+#define __ZYNQMP_TAP_DELAY_H__
+
+#ifdef CONFIG_ARCH_ZYNQMP
+void zynqmp_dll_reset(u8 deviceid);
+void arasan_zynqmp_set_tapdelay(u8 device_id, u8 uhsmode, u8 bank);
+#else
+inline void zynqmp_dll_reset(u8 deviceid) {}
+inline void arasan_zynqmp_set_tapdelay(u8 device_id, u8 uhsmode, u8 bank) {}
+#endif
+
+#endif
--
2.7.4
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