[U-Boot] [PATCH v2 1/8] armv8: Add workaround for USB erratum A-009008

[york sun]

On 01/30/2017 05:42 AM, Suresh Gupta wrote:
> From: Suresh Gupta <suresh.gupta at freescale.com>
>
> USB High Speed (HS) EYE Height Adjustment
> USB HS speed eye diagram fails with the default value at
> many corners, particularly at a high temperature
>
> Optimal eye at TXVREFTUNE value to 1001 is observed, change
> set the same vale.
>
> Signed-off-by: Sriram Dash <sriram.dash at nxp.com>
> Signed-off-by: Rajesh Bhagat <rajesh.bhagat at nxp.com>
> Signed-off-by: Suresh Gupta <suresh.gupta at nxp.com>
> ---
> Changes in v2: None
>
>  arch/arm/cpu/armv8/fsl-layerscape/Kconfig          |  6 ++++++
>  arch/arm/cpu/armv8/fsl-layerscape/soc.c            | 25 ++++++++++++++++++++++
>  .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |  6 ++++++
>  .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |  1 +
>  4 files changed, 38 insertions(+)
>
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> index de0b580..666a3d1 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> @@ -18,6 +18,7 @@ config ARCH_LS1043A
>  	select SYS_FSL_ERRATUM_A009942
>  	select SYS_FSL_ERRATUM_A010315
>  	select SYS_FSL_ERRATUM_A010539
> +	select SYS_FSL_ERRATUM_A009008
>  	select SYS_FSL_HAS_DDR3
>  	select SYS_FSL_HAS_DDR4
>
> @@ -33,6 +34,7 @@ config ARCH_LS1046A
>  	select SYS_FSL_ERRATUM_A009942
>  	select SYS_FSL_ERRATUM_A010165
>  	select SYS_FSL_ERRATUM_A010539
> +	select SYS_FSL_ERRATUM_A009008
>  	select SYS_FSL_HAS_DDR4
>  	select SYS_FSL_SRDS_2
>
> @@ -58,6 +60,7 @@ config ARCH_LS2080A
>  	select SYS_FSL_ERRATUM_A009803
>  	select SYS_FSL_ERRATUM_A009942
>  	select SYS_FSL_ERRATUM_A010165
> +	select SYS_FSL_ERRATUM_A009008
>
>  config FSL_LSCH2
>  	bool
> @@ -102,6 +105,9 @@ config SYS_FSL_ERRATUM_A010315
>  config SYS_FSL_ERRATUM_A010539
>  	bool "Workaround for PIN MUX erratum A010539"
>
> +config SYS_FSL_ERRATUM_A009008
> +	bool "Workaround for USB PHY erratum A009008"
> +
>  config MAX_CPUS
>  	int "Maximum number of CPUs permitted for Layerscape"
>  	default 4 if ARCH_LS1043A
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> index 2f54625..951ccba 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> @@ -52,6 +52,29 @@ bool soc_has_aiop(void)
>  	return false;
>  }
>
> +static void erratum_a009008(void)
> +{
> +#ifdef CONFIG_SYS_FSL_ERRATUM_A009008
> +#if defined(CONFIG_LS1043A) || defined(CONFIG_LS1046A)

Should this be CONFIG_FSL_LSCH2? If it has to be SoC name, use 
CONFIG_ARCH_LS1043A. Same comment goes to other patches in this set.

York