[U-Boot] [PATCH] rockchip: clk: rk3036: correct setting for pll integer mode

[Simon Glass]

On 6 June 2017 at 03:48, Kever Yang <kever.yang at rock-chips.com> wrote:
> According to rk3036 TRM, pll_con1[12] should be set to '1' for the pll
> interger mode, while the '0' means the frac mode.

Should that be 'integer' ?

>
> Signed-off-by: Kever Yang <kever.yang at rock-chips.com>
> ---
>
>  drivers/clk/rockchip/clk_rk3036.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)

Acked-by: Simon Glass <sjg at chromium.org>

>
> diff --git a/drivers/clk/rockchip/clk_rk3036.c b/drivers/clk/rockchip/clk_rk3036.c
> index d866d0b..8fefa19 100644
> --- a/drivers/clk/rockchip/clk_rk3036.c
> +++ b/drivers/clk/rockchip/clk_rk3036.c
> @@ -62,7 +62,7 @@ static int rkclk_set_pll(struct rk3036_cru *cru, enum rk_clk_id clk_id,
>                output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ);
>
>         /* use interger mode */

and here too

> -       rk_clrreg(&pll->con1, 1 << PLL_DSMPD_SHIFT);
> +       rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT);
>
>         rk_clrsetreg(&pll->con0,
>                      PLL_POSTDIV1_MASK << PLL_POSTDIV1_SHIFT | PLL_FBDIV_MASK,
> --
> 1.9.1
>