[U-Boot] [linux-sunxi] [RFC PATCH 5/8] sunxi: Add CPUCFG register definitions for A80/A83T SoCs

Icenowy Zheng icenowy at aosc.io
Wed Jun 7 03:44:58 UTC 2017



于 2017年6月7日 GMT+08:00 上午11:43:40, Chen-Yu Tsai <wens at csie.org> 写到:
>On Wed, Jun 7, 2017 at 8:47 AM, Icenowy Zheng <icenowy at aosc.io> wrote:
>> From: Chen-Yu Tsai <wens at csie.org>
>>
>> The A80/A83T SoCs has a different CPUCFG register layout, likely due
>to
>> having 2 clusters. The A83T SoC has also a small extra CPUCFG part
>> located at single cluster SoCs' CPUCFG address (in CPUs domain).
>>
>> Add a cpucfg header file for it, rename the original cpucfg.h to
>> cpucfg_sun4i.h and add a new cpucfg.h to automatically switch between
>> the two cpucfg header file.
>>
>> Signed-off-by: Chen-Yu Tsai <wens at csie.org>
>> Signed-off-by: Icenowy Zheng <icenowy at aosc.io>
>> ---
>>  arch/arm/include/asm/arch-sunxi/cpucfg.h       | 64
>+++---------------------
>>  arch/arm/include/asm/arch-sunxi/cpucfg_sun4i.h | 68
>++++++++++++++++++++++++++
>>  arch/arm/include/asm/arch-sunxi/cpucfg_sun9i.h | 60
>+++++++++++++++++++++++
>>  3 files changed, 134 insertions(+), 58 deletions(-)
>>  create mode 100644 arch/arm/include/asm/arch-sunxi/cpucfg_sun4i.h
>>  create mode 100644 arch/arm/include/asm/arch-sunxi/cpucfg_sun9i.h
>>
>> diff --git a/arch/arm/include/asm/arch-sunxi/cpucfg.h
>b/arch/arm/include/asm/arch-sunxi/cpucfg.h
>> index 297cdd28c0..cf60ff81b6 100644
>> --- a/arch/arm/include/asm/arch-sunxi/cpucfg.h
>> +++ b/arch/arm/include/asm/arch-sunxi/cpucfg.h
>> @@ -1,7 +1,5 @@
>>  /*
>> - * Sunxi A31 CPUCFG register definition.
>> - *
>> - * (C) Copyright 2014 Hans de Goede <hdegoede at redhat.com
>> + * (C) Copyright 2017 Icenowy Zheng <icenowy at aosc.io>
>>   *
>>   * SPDX-License-Identifier:    GPL-2.0+
>>   */
>> @@ -9,60 +7,10 @@
>>  #ifndef _SUNXI_CPUCFG_H
>>  #define _SUNXI_CPUCFG_H
>>
>> -#include <linux/compiler.h>
>> -#include <linux/types.h>
>> -
>> -#ifndef __ASSEMBLY__
>> -
>> -struct __packed sunxi_cpucfg_cpu {
>> -       u32 rst;                /* base + 0x0 */
>> -       u32 ctrl;               /* base + 0x4 */
>> -       u32 status;             /* base + 0x8 */
>> -       u8 res[0x34];           /* base + 0xc */
>> -};
>> -
>> -struct __packed sunxi_cpucfg_reg {
>> -       u8 res0[0x40];          /* 0x000 */
>> -       struct sunxi_cpucfg_cpu cpu[4];         /* 0x040 */
>> -       u8 res1[0x44];          /* 0x140 */
>> -       u32 gen_ctrl;           /* 0x184 */
>> -       u32 l2_status;          /* 0x188 */
>> -       u8 res2[0x4];           /* 0x18c */
>> -       u32 event_in;           /* 0x190 */
>> -       u8 res3[0xc];           /* 0x194 */
>> -       u32 super_standy_flag;  /* 0x1a0 */
>> -       u32 priv0;              /* 0x1a4 */
>> -       u32 priv1;              /* 0x1a8 */
>> -       u8 res4[0x4];           /* 0x1ac */
>> -       u32 cpu1_pwr_clamp;     /* 0x1b0 sun7i only */
>> -       u32 cpu1_pwroff;        /* 0x1b4 sun7i only */
>> -       u8 res5[0x2c];          /* 0x1b8 */
>> -       u32 dbg_ctrl1;          /* 0x1e4 */
>> -       u8 res6[0x18];          /* 0x1e8 */
>> -       u32 idle_cnt0_low;      /* 0x200 */
>> -       u32 idle_cnt0_high;     /* 0x204 */
>> -       u32 idle_cnt0_ctrl;     /* 0x208 */
>> -       u8 res8[0x4];           /* 0x20c */
>> -       u32 idle_cnt1_low;      /* 0x210 */
>> -       u32 idle_cnt1_high;     /* 0x214 */
>> -       u32 idle_cnt1_ctrl;     /* 0x218 */
>> -       u8 res9[0x4];           /* 0x21c */
>> -       u32 idle_cnt2_low;      /* 0x220 */
>> -       u32 idle_cnt2_high;     /* 0x224 */
>> -       u32 idle_cnt2_ctrl;     /* 0x228 */
>> -       u8 res10[0x4];          /* 0x22c */
>> -       u32 idle_cnt3_low;      /* 0x230 */
>> -       u32 idle_cnt3_high;     /* 0x234 */
>> -       u32 idle_cnt3_ctrl;     /* 0x238 */
>> -       u8 res11[0x4];          /* 0x23c */
>> -       u32 idle_cnt4_low;      /* 0x240 */
>> -       u32 idle_cnt4_high;     /* 0x244 */
>> -       u32 idle_cnt4_ctrl;     /* 0x248 */
>> -       u8 res12[0x34];         /* 0x24c */
>> -       u32 cnt64_ctrl;         /* 0x280 */
>> -       u32 cnt64_low;          /* 0x284 */
>> -       u32 cnt64_high;         /* 0x288 */
>> -};
>> +#if defined(CONFIG_MACH_SUN8I_A83T) || defined(CONFIG_MACH_SUN9I)
>> +#include <asm/arch/cpucfg_sun9i.h>
>> +#else
>> +#include <asm/arch/cpucfg_sun4i.h>
>> +#endif
>>
>> -#endif /* __ASSEMBLY__ */
>>  #endif /* _SUNXI_CPUCFG_H */
>> diff --git a/arch/arm/include/asm/arch-sunxi/cpucfg_sun4i.h
>b/arch/arm/include/asm/arch-sunxi/cpucfg_sun4i.h
>> new file mode 100644
>> index 0000000000..af1a1d56c9
>> --- /dev/null
>> +++ b/arch/arm/include/asm/arch-sunxi/cpucfg_sun4i.h
>> @@ -0,0 +1,68 @@
>> +/*
>> + * Sunxi A31 CPUCFG register definition.
>> + *
>> + * (C) Copyright 2014 Hans de Goede <hdegoede at redhat.com
>> + *
>> + * SPDX-License-Identifier:    GPL-2.0+
>> + */
>> +
>> +#ifndef _SUNXI_CPUCFG_SUN4I_H
>> +#define _SUNXI_CPUCFG_SUN4I_H
>> +
>> +#include <linux/compiler.h>
>> +#include <linux/types.h>
>> +
>> +#ifndef __ASSEMBLY__
>> +
>> +struct __packed sunxi_cpucfg_cpu {
>> +       u32 rst;                /* base + 0x0 */
>> +       u32 ctrl;               /* base + 0x4 */
>> +       u32 status;             /* base + 0x8 */
>> +       u8 res[0x34];           /* base + 0xc */
>> +};
>> +
>> +struct __packed sunxi_cpucfg_reg {
>> +       u8 res0[0x40];          /* 0x000 */
>> +       struct sunxi_cpucfg_cpu cpu[4];         /* 0x040 */
>> +       u8 res1[0x44];          /* 0x140 */
>> +       u32 gen_ctrl;           /* 0x184 */
>> +       u32 l2_status;          /* 0x188 */
>> +       u8 res2[0x4];           /* 0x18c */
>> +       u32 event_in;           /* 0x190 */
>> +       u8 res3[0xc];           /* 0x194 */
>> +       u32 super_standy_flag;  /* 0x1a0 */
>> +       u32 priv0;              /* 0x1a4 */
>> +       u32 priv1;              /* 0x1a8 */
>> +       u8 res4[0x4];           /* 0x1ac */
>> +       u32 cpu1_pwr_clamp;     /* 0x1b0 sun7i only */
>> +       u32 cpu1_pwroff;        /* 0x1b4 sun7i only */
>> +       u8 res5[0x2c];          /* 0x1b8 */
>> +       u32 dbg_ctrl1;          /* 0x1e4 */
>> +       u8 res6[0x18];          /* 0x1e8 */
>> +       u32 idle_cnt0_low;      /* 0x200 */
>> +       u32 idle_cnt0_high;     /* 0x204 */
>> +       u32 idle_cnt0_ctrl;     /* 0x208 */
>> +       u8 res8[0x4];           /* 0x20c */
>> +       u32 idle_cnt1_low;      /* 0x210 */
>> +       u32 idle_cnt1_high;     /* 0x214 */
>> +       u32 idle_cnt1_ctrl;     /* 0x218 */
>> +       u8 res9[0x4];           /* 0x21c */
>> +       u32 idle_cnt2_low;      /* 0x220 */
>> +       u32 idle_cnt2_high;     /* 0x224 */
>> +       u32 idle_cnt2_ctrl;     /* 0x228 */
>> +       u8 res10[0x4];          /* 0x22c */
>> +       u32 idle_cnt3_low;      /* 0x230 */
>> +       u32 idle_cnt3_high;     /* 0x234 */
>> +       u32 idle_cnt3_ctrl;     /* 0x238 */
>> +       u8 res11[0x4];          /* 0x23c */
>> +       u32 idle_cnt4_low;      /* 0x240 */
>> +       u32 idle_cnt4_high;     /* 0x244 */
>> +       u32 idle_cnt4_ctrl;     /* 0x248 */
>> +       u8 res12[0x34];         /* 0x24c */
>> +       u32 cnt64_ctrl;         /* 0x280 */
>> +       u32 cnt64_low;          /* 0x284 */
>> +       u32 cnt64_high;         /* 0x288 */
>> +};
>> +
>> +#endif /* __ASSEMBLY__ */
>> +#endif /* _SUNXI_CPUCFG_SUN4I_H */
>> diff --git a/arch/arm/include/asm/arch-sunxi/cpucfg_sun9i.h
>b/arch/arm/include/asm/arch-sunxi/cpucfg_sun9i.h
>> new file mode 100644
>> index 0000000000..2ce315736b
>> --- /dev/null
>> +++ b/arch/arm/include/asm/arch-sunxi/cpucfg_sun9i.h
>> @@ -0,0 +1,60 @@
>> +/*
>> + * Sunxi A80 CPUCFG register definition.
>> + *
>> + * (C) Copyright 2016 Chen-Yu Tsai <wens at csie.org>
>> + *
>> + * SPDX-License-Identifier:    GPL-2.0+
>> + */
>> +
>> +#ifndef _SUNXI_CPUCFG_SUN9I_H
>> +#define _SUNXI_CPUCFG_SUN9I_H
>> +
>> +#include <linux/compiler.h>
>> +#include <linux/types.h>
>> +
>> +#define CPUCFG_CX_CTRL0_L1_RST_DISABLE(core)   BIT(core)
>> +
>> +#define CPUCFG_CX_STATUS_STANDBYWFI(core)      BIT(16 + core)
>> +
>> +#define CPUCFG_CX_RST_CORE(core)               BIT(core)
>> +#define CPUCFG_CX_RST_NEON(core)               BIT(4 + core) /* A15
>only */
>> +#define CPUCFG_CX_RST_L2                       BIT(8)
>> +#define CPUCFG_CX_RST_HRESET                   BIT(12)
>> +#define CPUCFG_CX_RST_DBG(core)                        BIT(16 +
>core)
>> +#define CPUCFG_CX_RST_ETM(core)                        BIT(20 +
>core)
>> +#define CPUCFG_CX_RST_SOC_DBG                  BIT(24)
>> +
>> +#ifndef __ASSEMBLY__
>> +
>> +struct __packed sunxi_cpucfg_cluster {
>> +       u32 ctrl0;              /* base + 0x0 */
>> +       u32 ctrl1;              /* base + 0x4 */
>> +       u32 adb400_pwrdnreqn;   /* base + 0x8 */
>> +       u8 res[0x4];            /* base + 0xc */
>> +};
>> +
>> +struct __packed sunxi_cpucfg_reg {
>> +       struct sunxi_cpucfg_cluster cluster[2]; /* 0x00 */
>> +       u8 res0[0x8];           /* 0x20 */
>> +       u32 gen_ctrl0;          /* 0x28 */
>> +       u32 gen_ctrl1;          /* 0x2c */
>> +       u32 cluster_status[2];  /* 0x30 */
>> +       u8 res1[0x4];           /* 0x38 */
>> +       u32 irq_fiq_status;     /* 0x3c */
>> +       u32 irq_fiq_mask;       /* 0x40 */
>> +       u8 res2[0x3c];          /* 0x44 */
>> +       u32 cluster_reset[2];   /* 0x80 */
>> +       u32 gic_jtag_reset;     /* 0x88 */
>> +};
>> +
>> +#ifdef CONFIG_MACH_SUN8I_A83T
>> +struct __packed sunxi_r_cpucfg_reg {
>> +       u8 res1[0x30];          /* 0x00 */
>> +       u32 cpu_rst[2];         /* 0x30 */
>> +       u8 res2[0x16c];         /* 0x38 */
>> +       u32 priv0;              /* 0x1a4 */
>> +};
>> +#endif /* CONFIG_MACH_SUN8I_A83T */
>> +
>> +#endif /* __ASSEMBLY__ */
>> +#endif /* _SUNXI_CPUCFG_SUN9I_H */
>> --
>> 2.12.2
>
>This patch looks a bit weird. Do you have --find-renames and
>--find-copies
>set when you run `git format-patch`? It should help with renames.


Oh forget it...

Sorry.

>
>ChenYu


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