[U-Boot] [PATCH v3 2/4] mips: bmips: add bcm63xx-hsspi driver support for BCM6328

[Álvaro Fernández Rojas]

This driver manages the SPI controller present on this SoC.

Signed-off-by: Álvaro Fernández Rojas <noltari at gmail.com>
Reviewed-by: Simon Glass <sjg at chromium.org>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck at gmail.com>
---
 v3: no changes
 v2: no changes

 arch/mips/dts/brcm,bcm6328.dtsi | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/arch/mips/dts/brcm,bcm6328.dtsi b/arch/mips/dts/brcm,bcm6328.dtsi
index a996075..67d9278 100644
--- a/arch/mips/dts/brcm,bcm6328.dtsi
+++ b/arch/mips/dts/brcm,bcm6328.dtsi
@@ -13,6 +13,10 @@
 / {
 	compatible = "brcm,bcm6328";
 
+	aliases {
+		spi0 = &spi;
+	};
+
 	cpus {
 		reg = <0x10000000 0x4>;
 		#address-cells = <1>;
@@ -40,6 +44,12 @@
 		#size-cells = <1>;
 		u-boot,dm-pre-reloc;
 
+		hsspi_pll: hsspi-pll {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <133333333>;
+		};
+
 		periph_osc: periph-osc {
 			compatible = "fixed-clock";
 			#clock-cells = <0>;
@@ -123,6 +133,20 @@
 			status = "disabled";
 		};
 
+		spi: spi at 10001000 {
+			compatible = "brcm,bcm6328-hsspi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x10001000 0x600>;
+			clocks = <&periph_clk BCM6328_CLK_HSSPI>, <&hsspi_pll>;
+			clock-names = "hsspi", "pll";
+			resets = <&periph_rst BCM6328_RST_SPI>;
+			spi-max-frequency = <33333334>;
+			num-cs = <3>;
+
+			status = "disabled";
+		};
+
 		periph_pwr: power-controller at 10001848 {
 			compatible = "brcm,bcm6328-power-domain";
 			reg = <0x10001848 0x4>;
-- 
2.1.4