[U-Boot] [PATCH 04/11] Revert "powerpc, 5xx: remove support for 5xx"
Christophe Leroy
christophe.leroy at c-s.fr
Wed Jun 21 15:08:54 UTC 2017
This reverts commit 502589777416aaee32e4ba1682c6eb3aa3a88e1c.
Signed-off-by: Christophe Leroy <christophe.leroy at c-s.fr>
---
README | 12 +
api/api_platform-powerpc.c | 3 +-
arch/powerpc/Kconfig | 4 +
arch/powerpc/cpu/mpc5xx/Kconfig | 18 +
arch/powerpc/cpu/mpc5xx/Makefile | 20 ++
arch/powerpc/cpu/mpc5xx/config.mk | 8 +
arch/powerpc/cpu/mpc5xx/cpu.c | 156 +++++++++
arch/powerpc/cpu/mpc5xx/cpu_init.c | 108 ++++++
arch/powerpc/cpu/mpc5xx/interrupts.c | 192 +++++++++++
arch/powerpc/cpu/mpc5xx/serial.c | 168 ++++++++++
arch/powerpc/cpu/mpc5xx/speed.c | 52 +++
arch/powerpc/cpu/mpc5xx/spi.c | 396 ++++++++++++++++++++++
arch/powerpc/cpu/mpc5xx/start.S | 541 ++++++++++++++++++++++++++++++
arch/powerpc/cpu/mpc5xx/traps.c | 211 ++++++++++++
arch/powerpc/cpu/mpc5xx/u-boot.lds | 86 +++++
arch/powerpc/include/asm/5xx_immap.h | 424 +++++++++++++++++++++++
arch/powerpc/include/asm/ppc.h | 7 +-
arch/powerpc/include/asm/status_led.h | 73 ++++
arch/powerpc/lib/time.c | 11 +
board/mpl/common/common_util.c | 53 ++-
board/mpl/pati/Kconfig | 15 +
board/mpl/pati/MAINTAINERS | 6 +
board/mpl/pati/Makefile | 9 +
board/mpl/pati/cmd_pati.c | 433 ++++++++++++++++++++++++
board/mpl/pati/pati.c | 610 ++++++++++++++++++++++++++++++++++
board/mpl/pati/pati.h | 423 +++++++++++++++++++++++
board/mpl/pati/pci_eeprom.h | 90 +++++
board/mpl/pati/plx9056.h | 95 ++++++
cmd/bdinfo.c | 3 +-
cmd/reginfo.c | 37 +++
common/board_f.c | 3 +-
configs/PATI_defconfig | 28 ++
doc/README.mpc5xx | 48 +++
include/asm-generic/u-boot.h | 3 +-
include/configs/PATI.h | 245 ++++++++++++++
include/mpc5xx.h | 173 ++++++++++
include/ppc_asm.tmpl | 12 +
include/watchdog.h | 5 +
scripts/config_whitelist.txt | 18 +
39 files changed, 4792 insertions(+), 7 deletions(-)
create mode 100644 arch/powerpc/cpu/mpc5xx/Kconfig
create mode 100644 arch/powerpc/cpu/mpc5xx/Makefile
create mode 100644 arch/powerpc/cpu/mpc5xx/config.mk
create mode 100644 arch/powerpc/cpu/mpc5xx/cpu.c
create mode 100644 arch/powerpc/cpu/mpc5xx/cpu_init.c
create mode 100644 arch/powerpc/cpu/mpc5xx/interrupts.c
create mode 100644 arch/powerpc/cpu/mpc5xx/serial.c
create mode 100644 arch/powerpc/cpu/mpc5xx/speed.c
create mode 100644 arch/powerpc/cpu/mpc5xx/spi.c
create mode 100644 arch/powerpc/cpu/mpc5xx/start.S
create mode 100644 arch/powerpc/cpu/mpc5xx/traps.c
create mode 100644 arch/powerpc/cpu/mpc5xx/u-boot.lds
create mode 100644 arch/powerpc/include/asm/5xx_immap.h
create mode 100644 arch/powerpc/include/asm/status_led.h
create mode 100644 board/mpl/pati/Kconfig
create mode 100644 board/mpl/pati/MAINTAINERS
create mode 100644 board/mpl/pati/Makefile
create mode 100644 board/mpl/pati/cmd_pati.c
create mode 100644 board/mpl/pati/pati.c
create mode 100644 board/mpl/pati/pati.h
create mode 100644 board/mpl/pati/pci_eeprom.h
create mode 100644 board/mpl/pati/plx9056.h
create mode 100644 configs/PATI_defconfig
create mode 100644 doc/README.mpc5xx
create mode 100644 include/configs/PATI.h
create mode 100644 include/mpc5xx.h
diff --git a/README b/README
index 0833c41d48..99ee448a5e 100644
--- a/README
+++ b/README
@@ -4000,6 +4000,16 @@ Low Level (hardware related) configuration options:
point to an otherwise UNUSED address space between
the top of RAM and the start of the PCI space.
+- CONFIG_SYS_SIUMCR: SIU Module Configuration (11-6)
+
+- CONFIG_SYS_SYPCR: System Protection Control (11-9)
+
+- CONFIG_SYS_TBSCR: Time Base Status and Control (11-26)
+
+- CONFIG_SYS_PISCR: Periodic Interrupt Status and Control (11-31)
+
+- CONFIG_SYS_PLPRCR: PLL, Low-Power, and Reset Control Register (15-30)
+
- CONFIG_SYS_SCCR: System Clock and reset Control Register (15-27)
- CONFIG_SYS_OR_TIMING_SDRAM:
@@ -4008,6 +4018,8 @@ Low Level (hardware related) configuration options:
- CONFIG_SYS_MAMR_PTA:
periodic timer for refresh
+- CONFIG_SYS_DER: Debug Event Register (37-47)
+
- FLASH_BASE0_PRELIM, FLASH_BASE1_PRELIM, CONFIG_SYS_REMAP_OR_AM,
CONFIG_SYS_PRELIM_OR_AM, CONFIG_SYS_OR_TIMING_FLASH, CONFIG_SYS_OR0_REMAP,
CONFIG_SYS_OR0_PRELIM, CONFIG_SYS_BR0_PRELIM, CONFIG_SYS_OR1_REMAP, CONFIG_SYS_OR1_PRELIM,
diff --git a/api/api_platform-powerpc.c b/api/api_platform-powerpc.c
index 7d54ea7978..307a5f5bc4 100644
--- a/api/api_platform-powerpc.c
+++ b/api/api_platform-powerpc.c
@@ -30,7 +30,8 @@ int platform_sys_info(struct sys_info *si)
si->clk_bus = gd->bus_clk;
si->clk_cpu = gd->cpu_clk;
-#if defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
+#if defined(CONFIG_5xx) || \
+ defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
#define bi_bar bi_immr_base
#elif defined(CONFIG_MPC5xxx)
#define bi_bar bi_mbar_base
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index c0345acbf2..75594c6a99 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -11,6 +11,9 @@ choice
config MPC512X
bool "MPC512X"
+config 5xx
+ bool "MPC5xx"
+
config MPC5xxx
bool "MPC5xxx"
@@ -43,6 +46,7 @@ config 4xx
endchoice
source "arch/powerpc/cpu/mpc512x/Kconfig"
+source "arch/powerpc/cpu/mpc5xx/Kconfig"
source "arch/powerpc/cpu/mpc5xxx/Kconfig"
source "arch/powerpc/cpu/mpc83xx/Kconfig"
source "arch/powerpc/cpu/mpc85xx/Kconfig"
diff --git a/arch/powerpc/cpu/mpc5xx/Kconfig b/arch/powerpc/cpu/mpc5xx/Kconfig
new file mode 100644
index 0000000000..d81bfd2a50
--- /dev/null
+++ b/arch/powerpc/cpu/mpc5xx/Kconfig
@@ -0,0 +1,18 @@
+menu "mpc5xx CPU"
+ depends on 5xx
+
+config SYS_CPU
+ default "mpc5xx"
+
+choice
+ prompt "Target select"
+ optional
+
+config TARGET_PATI
+ bool "Support PATI"
+
+endchoice
+
+source "board/mpl/pati/Kconfig"
+
+endmenu
diff --git a/arch/powerpc/cpu/mpc5xx/Makefile b/arch/powerpc/cpu/mpc5xx/Makefile
new file mode 100644
index 0000000000..7b8826a643
--- /dev/null
+++ b/arch/powerpc/cpu/mpc5xx/Makefile
@@ -0,0 +1,20 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# (C) Copyright 2003
+# Martin Winistoerfer, martinwinistoerfer at gmx.ch.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+#
+# File: arch/powerpc/cpu/mpc5xx/Makefile
+#
+# Discription: Makefile to build mpc5xx cpu configuration.
+# Will include top config.mk which itselfs
+# uses the definitions made in arch/powerpc/cpu/mpc5xx/config.mk
+#
+
+extra-y = start.o
+obj-y = serial.o cpu.o cpu_init.o interrupts.o traps.o speed.o spi.o
diff --git a/arch/powerpc/cpu/mpc5xx/config.mk b/arch/powerpc/cpu/mpc5xx/config.mk
new file mode 100644
index 0000000000..dd2ec376c9
--- /dev/null
+++ b/arch/powerpc/cpu/mpc5xx/config.mk
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2003
+# Martin Winistoerfer, martinwinistoerfer at gmx.ch.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+PLATFORM_CPPFLAGS += -mpowerpc -msoft-float
diff --git a/arch/powerpc/cpu/mpc5xx/cpu.c b/arch/powerpc/cpu/mpc5xx/cpu.c
new file mode 100644
index 0000000000..cfcf633369
--- /dev/null
+++ b/arch/powerpc/cpu/mpc5xx/cpu.c
@@ -0,0 +1,156 @@
+/*
+ * (C) Copyright 2003
+ * Martin Winistoerfer, martinwinistoerfer at gmx.ch.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * File: cpu.c
+ *
+ * Discription: Some cpu specific function for watchdog,
+ * cpu version test, clock setting ...
+ *
+ */
+
+
+#include <common.h>
+#include <watchdog.h>
+#include <command.h>
+#include <mpc5xx.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if (defined(CONFIG_MPC555))
+# define ID_STR "MPC555/556"
+
+/*
+ * Check version of cpu with Processor Version Register (PVR)
+ */
+static int check_cpu_version (long clock, uint pvr, uint immr)
+{
+ char buf[32];
+ /* The highest 16 bits should be 0x0002 for a MPC555/556 */
+ if ((pvr >> 16) == 0x0002) {
+ printf (" " ID_STR " Version %x", (pvr >> 16));
+ printf (" at %s MHz:", strmhz (buf, clock));
+ } else {
+ printf ("Not supported cpu version");
+ return -1;
+ }
+ return 0;
+}
+#endif /* CONFIG_MPC555 */
+
+
+/*
+ * Check version of mpc5xx
+ */
+int checkcpu (void)
+{
+ ulong clock = gd->cpu_clk;
+ uint immr = get_immr (0); /* Return full IMMR contents */
+ uint pvr = get_pvr (); /* Retrieve PVR register */
+
+ puts ("CPU: ");
+
+ return check_cpu_version (clock, pvr, immr);
+}
+
+/*
+ * Called by macro WATCHDOG_RESET
+ */
+#if defined(CONFIG_WATCHDOG)
+void watchdog_reset (void)
+{
+ int re_enable = disable_interrupts ();
+
+ reset_5xx_watchdog ((immap_t *) CONFIG_SYS_IMMR);
+ if (re_enable)
+ enable_interrupts ();
+}
+
+/*
+ * Will clear software reset
+ */
+void reset_5xx_watchdog (volatile immap_t * immr)
+{
+ /* Use the MPC5xx Internal Watchdog */
+ immr->im_siu_conf.sc_swsr = 0x556c; /* Prevent SW time-out */
+ immr->im_siu_conf.sc_swsr = 0xaa39;
+}
+
+#endif /* CONFIG_WATCHDOG */
+
+
+/*
+ * Get timebase clock frequency
+ */
+unsigned long get_tbclk (void)
+{
+ volatile immap_t *immr = (volatile immap_t *) CONFIG_SYS_IMMR;
+ ulong oscclk, factor;
+
+ if (immr->im_clkrst.car_sccr & SCCR_TBS) {
+ return (gd->cpu_clk / 16);
+ }
+
+ factor = (((CONFIG_SYS_PLPRCR) & PLPRCR_MF_MSK) >> PLPRCR_MF_SHIFT) + 1;
+
+ oscclk = gd->cpu_clk / factor;
+
+ if ((immr->im_clkrst.car_sccr & SCCR_RTSEL) == 0 || factor > 2) {
+ return (oscclk / 4);
+ }
+ return (oscclk / 16);
+}
+
+void dcache_enable (void)
+{
+ return;
+}
+
+void dcache_disable (void)
+{
+ return;
+}
+
+int dcache_status (void)
+{
+ return 0; /* always off */
+}
+
+/*
+ * Reset board
+ */
+int do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+{
+#if defined(CONFIG_PATI)
+ volatile ulong *addr = (ulong *) CONFIG_SYS_RESET_ADDRESS;
+ *addr = 1;
+#else
+ ulong addr;
+
+ /* Interrupts off, enable reset */
+ __asm__ volatile (" mtspr 81, %r0 \n\t"
+ " mfmsr %r3 \n\t"
+ " rlwinm %r31,%r3,0,25,23\n\t"
+ " mtmsr %r31 \n\t");
+ /*
+ * Trying to execute the next instruction at a non-existing address
+ * should cause a machine check, resulting in reset
+ */
+#ifdef CONFIG_SYS_RESET_ADDRESS
+ addr = CONFIG_SYS_RESET_ADDRESS;
+#else
+ /*
+ * note: when CONFIG_SYS_MONITOR_BASE points to a RAM address, CONFIG_SYS_MONITOR_BASE * - sizeof (ulong) is usually a valid address. Better pick an address
+ * known to be invalid on your system and assign it to CONFIG_SYS_RESET_ADDRESS.
+ * "(ulong)-1" used to be a good choice for many systems...
+ */
+ addr = CONFIG_SYS_MONITOR_BASE - sizeof (ulong);
+#endif
+ ((void (*) (void)) addr) ();
+#endif /* #if defined(CONFIG_PATI) */
+ return 1;
+}
diff --git a/arch/powerpc/cpu/mpc5xx/cpu_init.c b/arch/powerpc/cpu/mpc5xx/cpu_init.c
new file mode 100644
index 0000000000..5bae39f8c0
--- /dev/null
+++ b/arch/powerpc/cpu/mpc5xx/cpu_init.c
@@ -0,0 +1,108 @@
+/*
+ * (C) Copyright 2003 Martin Winistoerfer, martinwinistoerfer at gmx.ch.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * File: cpu_init.c
+ *
+ * Discription: Contains initialisation functions to setup
+ * the cpu properly
+ *
+ */
+
+#include <common.h>
+#include <mpc5xx.h>
+#include <watchdog.h>
+
+/*
+ * Setup essential cpu registers to run
+ */
+void cpu_init_f (volatile immap_t * immr)
+{
+ volatile memctl5xx_t *memctl = &immr->im_memctl;
+ ulong reg;
+
+ /* SYPCR - contains watchdog control. This will enable watchdog */
+ /* if CONFIG_WATCHDOG is set */
+ immr->im_siu_conf.sc_sypcr = CONFIG_SYS_SYPCR;
+
+#if defined(CONFIG_WATCHDOG)
+ reset_5xx_watchdog (immr);
+#endif
+
+ /* SIUMCR - contains debug pin configuration */
+ immr->im_siu_conf.sc_siumcr |= CONFIG_SYS_SIUMCR;
+
+ /* Initialize timebase. Unlock TBSCRK */
+ immr->im_sitk.sitk_tbscrk = KAPWR_KEY;
+ immr->im_sit.sit_tbscr = CONFIG_SYS_TBSCR;
+
+ /* Full IMB bus speed */
+ immr->im_uimb.uimb_umcr = CONFIG_SYS_UMCR;
+
+ /* Time base and decrementer will be enables (TBE) */
+ /* in timer_init() in time.c called from board_init_f(). */
+
+ /* Initialize the PIT. Unlock PISCRK */
+ immr->im_sitk.sitk_piscrk = KAPWR_KEY;
+ immr->im_sit.sit_piscr = CONFIG_SYS_PISCR;
+
+#if !defined(CONFIG_PATI)
+ /* PATI sest PLL in start.S */
+ /* PLL (CPU clock) settings */
+ immr->im_clkrstk.cark_plprcrk = KAPWR_KEY;
+
+ /* If CONFIG_SYS_PLPRCR (set in the various *_config.h files) tries to
+ * set the MF field, then just copy CONFIG_SYS_PLPRCR over car_plprcr,
+ * otherwise OR in CONFIG_SYS_PLPRCR so we do not change the currentMF
+ * field value.
+ */
+#if ((CONFIG_SYS_PLPRCR & PLPRCR_MF_MSK) != 0)
+ reg = CONFIG_SYS_PLPRCR; /* reset control bits */
+#else
+ reg = immr->im_clkrst.car_plprcr;
+ reg &= PLPRCR_MF_MSK; /* isolate MF field */
+ reg |= CONFIG_SYS_PLPRCR; /* reset control bits */
+#endif
+ immr->im_clkrst.car_plprcr = reg;
+
+#endif /* !defined(CONFIG_PATI) */
+
+ /* System integration timers. CONFIG_SYS_MASK has EBDF configuration */
+ immr->im_clkrstk.cark_sccrk = KAPWR_KEY;
+ reg = immr->im_clkrst.car_sccr;
+ reg &= SCCR_MASK;
+ reg |= CONFIG_SYS_SCCR;
+ immr->im_clkrst.car_sccr = reg;
+
+ /* Memory Controller */
+ memctl->memc_br0 = CONFIG_SYS_BR0_PRELIM;
+ memctl->memc_or0 = CONFIG_SYS_OR0_PRELIM;
+
+#if (defined(CONFIG_SYS_OR1_PRELIM) && defined(CONFIG_SYS_BR1_PRELIM))
+ memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
+ memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
+#endif
+
+#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
+ memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM;
+ memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;
+#endif
+
+#if defined(CONFIG_SYS_OR3_PRELIM) && defined(CONFIG_SYS_BR3_PRELIM)
+ memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
+ memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
+#endif
+
+}
+
+/*
+ * Initialize higher level parts of cpu
+ */
+int cpu_init_r (void)
+{
+ /* Nothing to do at the moment */
+ return (0);
+}
diff --git a/arch/powerpc/cpu/mpc5xx/interrupts.c b/arch/powerpc/cpu/mpc5xx/interrupts.c
new file mode 100644
index 0000000000..35dddf5984
--- /dev/null
+++ b/arch/powerpc/cpu/mpc5xx/interrupts.c
@@ -0,0 +1,192 @@
+/*
+ * (C) Copyright 2000-2002 Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ * (C) Copyright 2003 Martin Winistoerfer, martinwinistoerfer at gmx.ch.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * File: interrupt.c
+ *
+ * Discription: Contains interrupt routines needed by U-Boot
+ *
+ */
+
+#include <common.h>
+#include <command.h>
+#include <mpc5xx.h>
+#include <asm/processor.h>
+
+#if defined(CONFIG_PATI)
+/* PATI uses IRQs for PCI doorbell */
+#undef NR_IRQS
+#define NR_IRQS 16
+#endif
+
+struct interrupt_action {
+ interrupt_handler_t *handler;
+ void *arg;
+ int count;
+};
+
+static struct interrupt_action irq_vecs[NR_IRQS];
+
+/*
+ * Initialise interrupts
+ */
+
+int interrupt_init_cpu (ulong *decrementer_count)
+{
+ volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
+ int vec;
+
+ /* Decrementer used here for status led */
+ *decrementer_count = get_tbclk () / CONFIG_SYS_HZ;
+
+ /* Disable all interrupts */
+ immr->im_siu_conf.sc_simask = 0;
+ for (vec=0; vec<NR_IRQS; vec++) {
+ irq_vecs[vec].handler = NULL;
+ irq_vecs[vec].arg = NULL;
+ irq_vecs[vec].count = 0;
+ }
+
+ return (0);
+}
+
+/*
+ * Handle external interrupts
+ */
+void external_interrupt (struct pt_regs *regs)
+{
+ volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
+ int irq;
+ ulong simask, newmask;
+ ulong vec, v_bit;
+
+ /*
+ * read the SIVEC register and shift the bits down
+ * to get the irq number
+ */
+ vec = immr->im_siu_conf.sc_sivec;
+ irq = vec >> 26;
+ v_bit = 0x80000000UL >> irq;
+
+ /*
+ * Read Interrupt Mask Register and Mask Interrupts
+ */
+ simask = immr->im_siu_conf.sc_simask;
+ newmask = simask & (~(0xFFFF0000 >> irq));
+ immr->im_siu_conf.sc_simask = newmask;
+
+ if (!(irq & 0x1)) { /* External Interrupt ? */
+ ulong siel;
+
+ /*
+ * Read Interrupt Edge/Level Register
+ */
+ siel = immr->im_siu_conf.sc_siel;
+
+ if (siel & v_bit) { /* edge triggered interrupt ? */
+ /*
+ * Rewrite SIPEND Register to clear interrupt
+ */
+ immr->im_siu_conf.sc_sipend = v_bit;
+ }
+ }
+
+ if (irq_vecs[irq].handler != NULL) {
+ irq_vecs[irq].handler (irq_vecs[irq].arg);
+ } else {
+ printf ("\nBogus External Interrupt IRQ %d Vector %ld\n",
+ irq, vec);
+ /* turn off the bogus interrupt to avoid it from now */
+ simask &= ~v_bit;
+ }
+ /*
+ * Re-Enable old Interrupt Mask
+ */
+ immr->im_siu_conf.sc_simask = simask;
+}
+
+/*
+ * Install and free an interrupt handler
+ */
+void irq_install_handler (int vec, interrupt_handler_t * handler,
+ void *arg)
+{
+ volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
+ /* SIU interrupt */
+ if (irq_vecs[vec].handler != NULL) {
+ printf ("SIU interrupt %d 0x%x\n",
+ vec,
+ (uint) handler);
+ }
+ irq_vecs[vec].handler = handler;
+ irq_vecs[vec].arg = arg;
+ immr->im_siu_conf.sc_simask |= 1 << (31 - vec);
+#if 0
+ printf ("Install SIU interrupt for vector %d ==> %p\n",
+ vec, handler);
+#endif
+}
+
+void irq_free_handler (int vec)
+{
+ volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
+ /* SIU interrupt */
+#if 0
+ printf ("Free CPM interrupt for vector %d\n",
+ vec);
+#endif
+ immr->im_siu_conf.sc_simask &= ~(1 << (31 - vec));
+ irq_vecs[vec].handler = NULL;
+ irq_vecs[vec].arg = NULL;
+}
+
+/*
+ * Timer interrupt - gets called when bit 0 of DEC changes from
+ * 0. Decrementer is enabled with bit TBE in TBSCR.
+ */
+void timer_interrupt_cpu (struct pt_regs *regs)
+{
+ volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
+
+#if 0
+ printf ("*** Timer Interrupt *** ");
+#endif
+ /* Reset Timer Status Bit and Timers Interrupt Status */
+ immr->im_clkrstk.cark_plprcrk = KAPWR_KEY;
+ __asm__ ("nop");
+ immr->im_clkrst.car_plprcr |= PLPRCR_TEXPS | PLPRCR_TMIST;
+
+ return;
+}
+
+#if defined(CONFIG_CMD_IRQ)
+/*******************************************************************************
+ *
+ * irqinfo - print information about IRQs
+ *
+ */
+int do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int vec;
+
+ printf ("\nInterrupt-Information:\n");
+ printf ("Nr Routine Arg Count\n");
+
+ for (vec=0; vec<NR_IRQS; vec++) {
+ if (irq_vecs[vec].handler != NULL) {
+ printf ("%02d %08lx %08lx %d\n",
+ vec,
+ (ulong)irq_vecs[vec].handler,
+ (ulong)irq_vecs[vec].arg,
+ irq_vecs[vec].count);
+ }
+ }
+ return 0;
+}
+
+
+#endif
diff --git a/arch/powerpc/cpu/mpc5xx/serial.c b/arch/powerpc/cpu/mpc5xx/serial.c
new file mode 100644
index 0000000000..a2a8d94e06
--- /dev/null
+++ b/arch/powerpc/cpu/mpc5xx/serial.c
@@ -0,0 +1,168 @@
+/*
+ * (C) Copyright 2003
+ * Martin Winistoerfer, martinwinistoerfer at gmx.ch.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * File: serial.c
+ *
+ * Discription: Serial interface driver for SCI1 and SCI2.
+ * Since this code will be called from ROM use
+ * only non-static local variables.
+ *
+ */
+
+#include <common.h>
+#include <watchdog.h>
+#include <command.h>
+#include <mpc5xx.h>
+#include <serial.h>
+#include <linux/compiler.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Local functions
+ */
+
+static int ready_to_send(void)
+{
+ volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+ volatile short status;
+
+ do {
+#if defined(CONFIG_5xx_CONS_SCI1)
+ status = immr->im_qsmcm.qsmcm_sc1sr;
+#else
+ status = immr->im_qsmcm.qsmcm_sc2sr;
+#endif
+
+#if defined(CONFIG_WATCHDOG)
+ reset_5xx_watchdog (immr);
+#endif
+ } while ((status & SCI_TDRE) == 0);
+ return 1;
+
+}
+
+/*
+ * Minimal global serial functions needed to use one of the SCI modules.
+ */
+
+static int mpc5xx_serial_init(void)
+{
+ volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+
+ serial_setbrg();
+
+#if defined(CONFIG_5xx_CONS_SCI1)
+ /* 10-Bit, 1 start bit, 8 data bit, no parity, 1 stop bit */
+ immr->im_qsmcm.qsmcm_scc1r1 = SCI_M_10;
+ immr->im_qsmcm.qsmcm_scc1r1 = SCI_TE | SCI_RE;
+#else
+ immr->im_qsmcm.qsmcm_scc2r1 = SCI_M_10;
+ immr->im_qsmcm.qsmcm_scc2r1 = SCI_TE | SCI_RE;
+#endif
+ return 0;
+}
+
+static void mpc5xx_serial_putc(const char c)
+{
+ volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+
+ /* Test for completition */
+ if(ready_to_send()) {
+#if defined(CONFIG_5xx_CONS_SCI1)
+ immr->im_qsmcm.qsmcm_sc1dr = (short)c;
+#else
+ immr->im_qsmcm.qsmcm_sc2dr = (short)c;
+#endif
+ if(c == '\n') {
+ if(ready_to_send());
+#if defined(CONFIG_5xx_CONS_SCI1)
+ immr->im_qsmcm.qsmcm_sc1dr = (short)'\r';
+#else
+ immr->im_qsmcm.qsmcm_sc2dr = (short)'\r';
+#endif
+ }
+ }
+}
+
+static int mpc5xx_serial_getc(void)
+{
+ volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+ volatile short status;
+ unsigned char tmp;
+
+ /* New data ? */
+ do {
+#if defined(CONFIG_5xx_CONS_SCI1)
+ status = immr->im_qsmcm.qsmcm_sc1sr;
+#else
+ status = immr->im_qsmcm.qsmcm_sc2sr;
+#endif
+
+#if defined(CONFIG_WATCHDOG)
+ reset_5xx_watchdog (immr);
+#endif
+ } while ((status & SCI_RDRF) == 0);
+
+ /* Read data */
+#if defined(CONFIG_5xx_CONS_SCI1)
+ tmp = (unsigned char)(immr->im_qsmcm.qsmcm_sc1dr & SCI_SCXDR_MK);
+#else
+ tmp = (unsigned char)( immr->im_qsmcm.qsmcm_sc2dr & SCI_SCXDR_MK);
+#endif
+ return tmp;
+}
+
+static int mpc5xx_serial_tstc(void)
+{
+ volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+ short status;
+
+ /* New data character ? */
+#if defined(CONFIG_5xx_CONS_SCI1)
+ status = immr->im_qsmcm.qsmcm_sc1sr;
+#else
+ status = immr->im_qsmcm.qsmcm_sc2sr;
+#endif
+ return (status & SCI_RDRF);
+}
+
+static void mpc5xx_serial_setbrg(void)
+{
+ volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+ short scxbr;
+
+ /* Set baudrate */
+ scxbr = (gd->cpu_clk / (32 * gd->baudrate));
+#if defined(CONFIG_5xx_CONS_SCI1)
+ immr->im_qsmcm.qsmcm_scc1r0 = (scxbr & SCI_SCXBR_MK);
+#else
+ immr->im_qsmcm.qsmcm_scc2r0 = (scxbr & SCI_SCXBR_MK);
+#endif
+}
+
+static struct serial_device mpc5xx_serial_drv = {
+ .name = "mpc5xx_serial",
+ .start = mpc5xx_serial_init,
+ .stop = NULL,
+ .setbrg = mpc5xx_serial_setbrg,
+ .putc = mpc5xx_serial_putc,
+ .puts = default_serial_puts,
+ .getc = mpc5xx_serial_getc,
+ .tstc = mpc5xx_serial_tstc,
+};
+
+void mpc5xx_serial_initialize(void)
+{
+ serial_register(&mpc5xx_serial_drv);
+}
+
+__weak struct serial_device *default_serial_console(void)
+{
+ return &mpc5xx_serial_drv;
+}
diff --git a/arch/powerpc/cpu/mpc5xx/speed.c b/arch/powerpc/cpu/mpc5xx/speed.c
new file mode 100644
index 0000000000..24b9026f56
--- /dev/null
+++ b/arch/powerpc/cpu/mpc5xx/speed.c
@@ -0,0 +1,52 @@
+/*
+ * (C) Copyright 2003
+ * Martin Winistoerfer, martinwinistoerfer at gmx.ch.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * File: speed.c
+ *
+ * Discription: Provides cpu speed calculation
+ *
+ */
+
+#include <common.h>
+#include <mpc5xx.h>
+#include <asm/processor.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Get cpu and bus clock
+ */
+int get_clocks (void)
+{
+ volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
+
+#ifndef CONFIG_5xx_GCLK_FREQ
+ uint divf = (immr->im_clkrst.car_plprcr & PLPRCR_DIVF_MSK);
+ uint mf = ((immr->im_clkrst.car_plprcr & PLPRCR_MF_MSK) >> PLPRCR_MF_SHIFT);
+ ulong vcoout;
+
+ vcoout = (CONFIG_SYS_OSC_CLK / (divf + 1)) * (mf + 1) * 2;
+ if(immr->im_clkrst.car_plprcr & PLPRCR_CSRC_MSK) {
+ gd->cpu_clk = vcoout / (2^(((immr->im_clkrst.car_sccr & SCCR_DFNL_MSK) >> SCCR_DFNL_SHIFT) + 1));
+ } else {
+ gd->cpu_clk = vcoout / (2^(immr->im_clkrst.car_sccr & SCCR_DFNH_MSK));
+ }
+
+#else /* CONFIG_5xx_GCLK_FREQ */
+ gd->bus_clk = CONFIG_5xx_GCLK_FREQ;
+#endif /* CONFIG_5xx_GCLK_FREQ */
+
+ if ((immr->im_clkrst.car_sccr & SCCR_EBDF11) == 0) {
+ /* No Bus Divider active */
+ gd->bus_clk = gd->cpu_clk;
+ } else {
+ /* CLKOUT is GCLK / 2 */
+ gd->bus_clk = gd->cpu_clk / 2;
+ }
+ return (0);
+}
diff --git a/arch/powerpc/cpu/mpc5xx/spi.c b/arch/powerpc/cpu/mpc5xx/spi.c
new file mode 100644
index 0000000000..ef8b55f5f0
--- /dev/null
+++ b/arch/powerpc/cpu/mpc5xx/spi.c
@@ -0,0 +1,396 @@
+/*
+ * Copyright (c) 2001 Navin Boppuri / Prashant Patel
+ * <nboppuri at trinetcommunication.com>,
+ * <pmpatel at trinetcommunication.com>
+ * Copyright (c) 2001 Gerd Mennchen <Gerd.Mennchen at icn.siemens.de>
+ * Copyright (c) 2001 Wolfgang Denk, DENX Software Engineering, <wd at denx.de>.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * MPC5xx CPM SPI interface.
+ *
+ * Parts of this code are probably not portable and/or specific to
+ * the board which I used for the tests. Please send fixes/complaints
+ * to wd at denx.de
+ *
+ * Ported to MPC5xx
+ * Copyright (c) 2003 Denis Peter, MPL AG Switzerland, d.petr at mpl.ch.
+ */
+
+#include <common.h>
+#include <mpc5xx.h>
+#include <asm/5xx_immap.h>
+#include <linux/ctype.h>
+#include <malloc.h>
+#include <post.h>
+#include <net.h>
+
+#if defined(CONFIG_SPI)
+
+#undef DEBUG
+
+#define SPI_EEPROM_WREN 0x06
+#define SPI_EEPROM_RDSR 0x05
+#define SPI_EEPROM_READ 0x03
+#define SPI_EEPROM_WRITE 0x02
+
+
+#ifdef DEBUG
+
+#define DPRINT(a) printf a;
+/* -----------------------------------------------
+ * Helper functions to peek into tx and rx buffers
+ * ----------------------------------------------- */
+static const char * const hex_digit = "0123456789ABCDEF";
+
+static char quickhex (int i)
+{
+ return hex_digit[i];
+}
+
+static void memdump (void *pv, int num)
+{
+ int i;
+ unsigned char *pc = (unsigned char *) pv;
+
+ for (i = 0; i < num; i++)
+ printf ("%c%c ", quickhex (pc[i] >> 4), quickhex (pc[i] & 0x0f));
+ printf ("\t");
+ for (i = 0; i < num; i++)
+ printf ("%c", isprint (pc[i]) ? pc[i] : '.');
+ printf ("\n");
+}
+#else /* !DEBUG */
+
+#define DPRINT(a)
+
+#endif /* DEBUG */
+
+/* -------------------
+ * Function prototypes
+ * ------------------- */
+void spi_init (void);
+
+ssize_t spi_read (uchar *, int, uchar *, int);
+ssize_t spi_write (uchar *, int, uchar *, int);
+ssize_t spi_xfer (size_t);
+
+
+/* **************************************************************************
+ *
+ * Function: spi_init_f
+ *
+ * Description: Init SPI-Controller (ROM part)
+ *
+ * return: ---
+ *
+ * *********************************************************************** */
+
+void spi_init_f (void)
+{
+ int i;
+
+ volatile immap_t *immr;
+ volatile qsmcm5xx_t *qsmcm;
+
+ immr = (immap_t *) CONFIG_SYS_IMMR;
+ qsmcm = (qsmcm5xx_t *)&immr->im_qsmcm;
+
+ qsmcm->qsmcm_qsmcr = 0; /* all accesses enabled */
+ qsmcm->qsmcm_qspi_il = 0; /* lowest IRQ */
+
+ /* --------------------------------------------
+ * GPIO or per. Function
+ * PQSPAR[00] = 0 reserved
+ * PQSPAR[01] = 1 [0x4000] -> PERI: (SPICS3)
+ * PQSPAR[02] = 0 [0x0000] -> GPIO
+ * PQSPAR[03] = 0 [0x0000] -> GPIO
+ * PQSPAR[04] = 1 [0x0800] -> PERI: (SPICS0)
+ * PQSPAR[05] = 0 reseved
+ * PQSPAR[06] = 1 [0x0200] -> PERI: (SPIMOSI)
+ * PQSPAR[07] = 1 [0x0100] -> PERI: (SPIMISO)
+ * -------------------------------------------- */
+ qsmcm->qsmcm_pqspar = 0x3 | (CONFIG_SYS_SPI_CS_USED << 3);
+
+ /* --------------------------------------------
+ * DDRQS[00] = 0 reserved
+ * DDRQS[01] = 1 [0x0040] -> SPICS3 Output
+ * DDRQS[02] = 0 [0x0000] -> GPIO Output
+ * DDRQS[03] = 0 [0x0000] -> GPIO Output
+ * DDRQS[04] = 1 [0x0008] -> SPICS0 Output
+ * DDRQS[05] = 1 [0x0004] -> SPICLK Output
+ * DDRQS[06] = 1 [0x0002] -> SPIMOSI Output
+ * DDRQS[07] = 0 [0x0001] -> SPIMISO Input
+ * -------------------------------------------- */
+ qsmcm->qsmcm_ddrqs = 0x7E;
+ /* --------------------------------------------
+ * Base state for used SPI CS pins, if base = 0 active must be 1
+ * PORTQS[00] = 0 reserved
+ * PORTQS[01] = 0 reserved
+ * PORTQS[02] = 0 reserved
+ * PORTQS[03] = 0 reserved
+ * PORTQS[04] = 0 [0x0000] RxD2
+ * PORTQS[05] = 1 [0x0400] TxD2
+ * PORTQS[06] = 0 [0x0000] RxD1
+ * PORTQS[07] = 1 [0x0100] TxD1
+ * PORTQS[08] = 0 reserved
+ * PORTQS[09] = 0 [0x0000] -> SPICS3 Base Output
+ * PORTQS[10] = 0 [0x0000] -> SPICS2 Base Output
+ * PORTQS[11] = 0 [0x0000] -> SPICS1 Base Output
+ * PORTQS[12] = 0 [0x0000] -> SPICS0 Base Output
+ * PORTQS[13] = 0 [0x0004] -> SPICLK Output
+ * PORTQS[14] = 0 [0x0002] -> SPIMOSI Output
+ * PORTQS[15] = 0 [0x0001] -> SPIMISO Input
+ * -------------------------------------------- */
+ qsmcm->qsmcm_portqs |= (CONFIG_SYS_SPI_CS_BASE << 3);
+ /* --------------------------------------------
+ * Controll Register 0
+ * SPCR0[00] = 1 (0x8000) Master
+ * SPCR0[01] = 0 (0x0000) Wired-Or
+ * SPCR0[2..5] = (0x2000) Bits per transfer (default 8)
+ * SPCR0[06] = 0 (0x0000) Normal polarity
+ * SPCR0[07] = 0 (0x0000) Normal Clock Phase
+ * SPCR0[08..15] = 14 1.4MHz
+ */
+ qsmcm->qsmcm_spcr0=0xA00E;
+ /* --------------------------------------------
+ * Controll Register 1
+ * SPCR1[00] = 0 (0x0000) QSPI enabled
+ * SPCR1[1..7] = (0x7F00) Delay before Transfer
+ * SPCR1[8..15] = (0x0000) Delay After transfer (204.8usec at 40MHz)
+ */
+ qsmcm->qsmcm_spcr1=0x7F00;
+ /* --------------------------------------------
+ * Controll Register 2
+ * SPCR2[00] = 0 (0x0000) SPI IRQs Disabeld
+ * SPCR2[01] = 0 (0x0000) No Wrap around
+ * SPCR2[02] = 0 (0x0000) Wrap to 0
+ * SPCR2[3..7] = (0x0000) End Queue pointer = 0
+ * SPCR2[8..10] = 0 (0x0000) reserved
+ * SPCR2[11..15] = 0 (0x0000) NewQueue Address = 0
+ */
+ qsmcm->qsmcm_spcr2=0x0000;
+ /* --------------------------------------------
+ * Controll Register 3
+ * SPCR3[00..04] = 0 (0x0000) reserved
+ * SPCR3[05] = 0 (0x0000) Feedback disabled
+ * SPCR3[06] = 0 (0x0000) IRQ on HALTA & MODF disabled
+ * SPCR3[07] = 0 (0x0000) Not halted
+ */
+ qsmcm->qsmcm_spcr3=0x00;
+ /* --------------------------------------------
+ * SPSR (Controll Register 3) Read only/ reset Flags 08,09,10
+ * SPCR3[08] = 1 (0x80) QSPI finished
+ * SPCR3[09] = 1 (0x40) Mode Fault Flag
+ * SPCR3[10] = 1 (0x20) HALTA
+ * SPCR3[11..15] = 0 (0x0000) Last executed command
+ */
+ qsmcm->qsmcm_spsr=0xE0;
+ /*-------------------------------------------
+ * Setup RAM
+ */
+ for(i=0;i<32;i++) {
+ qsmcm->qsmcm_recram[i]=0x0000;
+ qsmcm->qsmcm_tranram[i]=0x0000;
+ qsmcm->qsmcm_comdram[i]=0x00;
+ }
+ return;
+}
+
+/* **************************************************************************
+ *
+ * Function: spi_init_r
+ * Dummy, all initializations have been done in spi_init_r
+ * *********************************************************************** */
+void spi_init_r (void)
+{
+ return;
+
+}
+
+/****************************************************************************
+ * Function: spi_write
+ **************************************************************************** */
+ssize_t short_spi_write (uchar *addr, int alen, uchar *buffer, int len)
+{
+ int i,dlen;
+ volatile immap_t *immr;
+ volatile qsmcm5xx_t *qsmcm;
+
+ immr = (immap_t *) CONFIG_SYS_IMMR;
+ qsmcm = (qsmcm5xx_t *)&immr->im_qsmcm;
+ for(i=0;i<32;i++) {
+ qsmcm->qsmcm_recram[i]=0x0000;
+ qsmcm->qsmcm_tranram[i]=0x0000;
+ qsmcm->qsmcm_comdram[i]=0x00;
+ }
+ qsmcm->qsmcm_tranram[0] = SPI_EEPROM_WREN; /* write enable */
+ spi_xfer(1);
+ i=0;
+ qsmcm->qsmcm_tranram[i++] = SPI_EEPROM_WRITE; /* WRITE memory array */
+ qsmcm->qsmcm_tranram[i++] = addr[0];
+ qsmcm->qsmcm_tranram[i++] = addr[1];
+
+ for(dlen=0;dlen<len;dlen++) {
+ qsmcm->qsmcm_tranram[i+dlen] = buffer[dlen]; /* WRITE memory array */
+ }
+ /* transmit it */
+ spi_xfer(i+dlen);
+ /* ignore received data */
+ for (i = 0; i < 1000; i++) {
+ qsmcm->qsmcm_tranram[0] = SPI_EEPROM_RDSR; /* read status */
+ qsmcm->qsmcm_tranram[1] = 0;
+ spi_xfer(2);
+ if (!(qsmcm->qsmcm_recram[1] & 1)) {
+ break;
+ }
+ udelay(1000);
+ }
+ if (i >= 1000) {
+ printf ("*** spi_write: Time out while writing!\n");
+ }
+ return len;
+}
+
+#define TRANSFER_LEN 16
+
+ssize_t spi_write (uchar *addr, int alen, uchar *buffer, int len)
+{
+ int index,i,newlen;
+ uchar newaddr[2];
+ int curraddr;
+
+ curraddr=(addr[alen-2]<<8)+addr[alen-1];
+ i=len;
+ index=0;
+ do {
+ newaddr[1]=(curraddr & 0xff);
+ newaddr[0]=((curraddr>>8) & 0xff);
+ if(i>TRANSFER_LEN) {
+ newlen=TRANSFER_LEN;
+ i-=TRANSFER_LEN;
+ }
+ else {
+ newlen=i;
+ i=0;
+ }
+ short_spi_write (newaddr, 2, &buffer[index], newlen);
+ index+=newlen;
+ curraddr+=newlen;
+ }while(i);
+ return (len);
+}
+
+/****************************************************************************
+ * Function: spi_read
+ **************************************************************************** */
+ssize_t short_spi_read (uchar *addr, int alen, uchar *buffer, int len)
+{
+ int i;
+ volatile immap_t *immr;
+ volatile qsmcm5xx_t *qsmcm;
+
+ immr = (immap_t *) CONFIG_SYS_IMMR;
+ qsmcm = (qsmcm5xx_t *)&immr->im_qsmcm;
+
+ for(i=0;i<32;i++) {
+ qsmcm->qsmcm_recram[i]=0x0000;
+ qsmcm->qsmcm_tranram[i]=0x0000;
+ qsmcm->qsmcm_comdram[i]=0x00;
+ }
+ i=0;
+ qsmcm->qsmcm_tranram[i++] = (SPI_EEPROM_READ); /* READ memory array */
+ qsmcm->qsmcm_tranram[i++] = addr[0] & 0xff;
+ qsmcm->qsmcm_tranram[i++] = addr[1] & 0xff;
+ spi_xfer(3 + len);
+ for(i=0;i<len;i++) {
+ *buffer++=(char)qsmcm->qsmcm_recram[i+3];
+ }
+ return len;
+}
+
+ssize_t spi_read (uchar *addr, int alen, uchar *buffer, int len)
+{
+ int index,i,newlen;
+ uchar newaddr[2];
+ int curraddr;
+
+ curraddr=(addr[alen-2]<<8)+addr[alen-1];
+ i=len;
+ index=0;
+ do {
+ newaddr[1]=(curraddr & 0xff);
+ newaddr[0]=((curraddr>>8) & 0xff);
+ if(i>TRANSFER_LEN) {
+ newlen=TRANSFER_LEN;
+ i-=TRANSFER_LEN;
+ }
+ else {
+ newlen=i;
+ i=0;
+ }
+ short_spi_read (newaddr, 2, &buffer[index], newlen);
+ index+=newlen;
+ curraddr+=newlen;
+ }while(i);
+ return (len);
+}
+
+/****************************************************************************
+ * Function: spi_xfer
+ **************************************************************************** */
+ssize_t spi_xfer (size_t count)
+{
+ volatile immap_t *immr;
+ volatile qsmcm5xx_t *qsmcm;
+ int i;
+ int tm;
+ ushort status;
+ immr = (immap_t *) CONFIG_SYS_IMMR;
+ qsmcm = (qsmcm5xx_t *)&immr->im_qsmcm;
+ DPRINT (("*** spi_xfer entered count %d***\n",count));
+
+ /* Set CS for device */
+ for(i=0;i<(count-1);i++)
+ qsmcm->qsmcm_comdram[i] = 0x80 | CONFIG_SYS_SPI_CS_ACT; /* CS3 is connected to the SPI EEPROM */
+
+ qsmcm->qsmcm_comdram[i] = CONFIG_SYS_SPI_CS_ACT; /* CS3 is connected to the SPI EEPROM */
+ qsmcm->qsmcm_spcr2=((count-1)&0x1F)<<8;
+
+ DPRINT (("*** spi_xfer: Bytes to be xferred: %d ***\n", count));
+
+ qsmcm->qsmcm_spsr=0xE0; /* clear all flags */
+
+ /* start spi transfer */
+ DPRINT (("*** spi_xfer: Performing transfer ...\n"));
+ qsmcm->qsmcm_spcr1 |= 0x8000; /* Start transmit */
+
+ /* --------------------------------
+ * Wait for SPI transmit to get out
+ * or time out (1 second = 1000 ms)
+ * -------------------------------- */
+ for (tm=0; tm<1000; ++tm) {
+ status=qsmcm->qsmcm_spcr1;
+ if((status & 0x8000)==0)
+ break;
+ udelay (1000);
+ }
+ if (tm >= 1000) {
+ printf ("*** spi_xfer: Time out while xferring to/from SPI!\n");
+ }
+#ifdef DEBUG
+ printf ("\nspi_xfer: txbuf after xfer\n");
+ memdump ((void *) qsmcm->qsmcm_tranram, 32); /* dump of txbuf before transmit */
+ printf ("spi_xfer: rxbuf after xfer\n");
+ memdump ((void *) qsmcm->qsmcm_recram, 32); /* dump of rxbuf after transmit */
+ printf ("\nspi_xfer: commbuf after xfer\n");
+ memdump ((void *) qsmcm->qsmcm_comdram, 32); /* dump of txbuf before transmit */
+ printf ("\n");
+#endif
+
+ return count;
+}
+
+#endif /* CONFIG_SPI */
diff --git a/arch/powerpc/cpu/mpc5xx/start.S b/arch/powerpc/cpu/mpc5xx/start.S
new file mode 100644
index 0000000000..6b196de355
--- /dev/null
+++ b/arch/powerpc/cpu/mpc5xx/start.S
@@ -0,0 +1,541 @@
+/*
+ * Copyright (C) 1998 Dan Malek <dmalek at jlc.net>
+ * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
+ * Copyright (C) 2000, 2001, 2002 Wolfgang Denk <wd at denx.de>
+ * Copyright (C) 2003 Martin Winistoerfer, martinwinistoerfer at gmx.ch.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * File: start.S
+ *
+ * Discription: startup code
+ *
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <mpc5xx.h>
+#include <version.h>
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+
+#include <asm/processor.h>
+#include <asm/u-boot.h>
+
+/* We don't have a MMU.
+*/
+#undef MSR_KERNEL
+#define MSR_KERNEL ( MSR_ME | MSR_RI ) /* Machine Check and Recoverable Interr. */
+
+/*
+ * Set up GOT: Global Offset Table
+ *
+ * Use r12 to access the GOT
+ */
+ START_GOT
+ GOT_ENTRY(_GOT2_TABLE_)
+ GOT_ENTRY(_FIXUP_TABLE_)
+
+ GOT_ENTRY(_start)
+ GOT_ENTRY(_start_of_vectors)
+ GOT_ENTRY(_end_of_vectors)
+ GOT_ENTRY(transfer_to_handler)
+
+ GOT_ENTRY(__init_end)
+ GOT_ENTRY(__bss_end)
+ GOT_ENTRY(__bss_start)
+ END_GOT
+
+/*
+ * r3 - 1st arg to board_init(): IMMP pointer
+ * r4 - 2nd arg to board_init(): boot flag
+ */
+ .text
+ .long 0x27051956 /* U-Boot Magic Number */
+ .globl version_string
+version_string:
+ .ascii U_BOOT_VERSION_STRING, "\0"
+
+ . = EXC_OFF_SYS_RESET
+ .globl _start
+_start:
+ mfspr r3, 638
+ li r4, CONFIG_SYS_ISB /* Set ISB bit */
+ or r3, r3, r4
+ mtspr 638, r3
+
+ /* Initialize machine status; enable machine check interrupt */
+ /*----------------------------------------------------------------------*/
+ li r3, MSR_KERNEL /* Set ME, RI flags */
+ mtmsr r3
+ mtspr SRR1, r3 /* Make SRR1 match MSR */
+
+ /* Initialize debug port registers */
+ /*----------------------------------------------------------------------*/
+ xor r0, r0, r0 /* Clear R0 */
+ mtspr LCTRL1, r0 /* Initialize debug port regs */
+ mtspr LCTRL2, r0
+ mtspr COUNTA, r0
+ mtspr COUNTB, r0
+
+#if defined(CONFIG_PATI)
+ /* the external flash access on PATI fails if programming the PLL to 40MHz.
+ * Copy the PLL programming code to the internal RAM and execute it
+ *----------------------------------------------------------------------*/
+ lis r3, CONFIG_SYS_MONITOR_BASE at h
+ ori r3, r3, CONFIG_SYS_MONITOR_BASE at l
+ addi r3, r3, pll_prog_code_start - _start + EXC_OFF_SYS_RESET
+
+ lis r4, CONFIG_SYS_INIT_RAM_ADDR at h
+ ori r4, r4, CONFIG_SYS_INIT_RAM_ADDR at l
+ mtlr r4
+ addis r5,0,0x0
+ ori r5,r5,((pll_prog_code_end - pll_prog_code_start) >>2)
+ mtctr r5
+ addi r3, r3, -4
+ addi r4, r4, -4
+0:
+ lwzu r0,4(r3)
+ stwu r0,4(r4)
+ bdnz 0b /* copy loop */
+ blrl
+#endif
+
+ /*
+ * Calculate absolute address in FLASH and jump there
+ *----------------------------------------------------------------------*/
+
+ lis r3, CONFIG_SYS_MONITOR_BASE at h
+ ori r3, r3, CONFIG_SYS_MONITOR_BASE at l
+ addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
+ mtlr r3
+ blr
+
+in_flash:
+
+ /* Initialize some SPRs that are hard to access from C */
+ /*----------------------------------------------------------------------*/
+
+ lis r3, CONFIG_SYS_IMMR at h /* Pass IMMR as arg1 to C routine */
+ lis r2, CONFIG_SYS_INIT_SP_ADDR at h
+ ori r1, r2, CONFIG_SYS_INIT_SP_ADDR at l /* Set up the stack in internal SRAM */
+ /* Note: R0 is still 0 here */
+ stwu r0, -4(r1) /* Clear final stack frame so that */
+ stwu r0, -4(r1) /* stack backtraces terminate cleanly */
+
+ /*
+ * Disable serialized ifetch and show cycles
+ * (i.e. set processor to normal mode) for maximum
+ * performance.
+ */
+
+ li r2, 0x0007
+ mtspr ICTRL, r2
+
+ /* Set up debug mode entry */
+
+ lis r2, CONFIG_SYS_DER at h
+ ori r2, r2, CONFIG_SYS_DER at l
+ mtspr DER, r2
+
+ /* Let the C-code set up the rest */
+ /* */
+ /* Be careful to keep code relocatable ! */
+ /*----------------------------------------------------------------------*/
+
+ GET_GOT /* initialize GOT access */
+
+ /* r3: IMMR */
+ bl cpu_init_f /* run low-level CPU init code (from Flash) */
+
+ bl board_init_f /* run 1st part of board init code (from Flash) */
+
+ /* NOTREACHED - board_init_f() does not return */
+
+
+ .globl _start_of_vectors
+_start_of_vectors:
+
+/* Machine check */
+ STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
+
+/* Data Storage exception. "Never" generated on the 860. */
+ STD_EXCEPTION(0x300, DataStorage, UnknownException)
+
+/* Instruction Storage exception. "Never" generated on the 860. */
+ STD_EXCEPTION(0x400, InstStorage, UnknownException)
+
+/* External Interrupt exception. */
+ STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
+
+/* Alignment exception. */
+ . = 0x600
+Alignment:
+ EXCEPTION_PROLOG(SRR0, SRR1)
+ mfspr r4,DAR
+ stw r4,_DAR(r21)
+ mfspr r5,DSISR
+ stw r5,_DSISR(r21)
+ addi r3,r1,STACK_FRAME_OVERHEAD
+ EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
+
+/* Program check exception */
+ . = 0x700
+ProgramCheck:
+ EXCEPTION_PROLOG(SRR0, SRR1)
+ addi r3,r1,STACK_FRAME_OVERHEAD
+ EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
+ MSR_KERNEL, COPY_EE)
+
+ /* FPU on MPC5xx available. We will use it later.
+ */
+ STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
+
+ /* I guess we could implement decrementer, and may have
+ * to someday for timekeeping.
+ */
+ STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
+ STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
+ STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
+ STD_EXCEPTION(0xc00, SystemCall, UnknownException)
+ STD_EXCEPTION(0xd00, SingleStep, UnknownException)
+
+ STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
+ STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
+
+ /* On the MPC8xx, this is a software emulation interrupt. It occurs
+ * for all unimplemented and illegal instructions.
+ */
+ STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException)
+ STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
+ STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
+ STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException)
+ STD_EXCEPTION(0x1400, DataTLBError, UnknownException)
+
+ STD_EXCEPTION(0x1500, Reserved5, UnknownException)
+ STD_EXCEPTION(0x1600, Reserved6, UnknownException)
+ STD_EXCEPTION(0x1700, Reserved7, UnknownException)
+ STD_EXCEPTION(0x1800, Reserved8, UnknownException)
+ STD_EXCEPTION(0x1900, Reserved9, UnknownException)
+ STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
+ STD_EXCEPTION(0x1b00, ReservedB, UnknownException)
+
+ STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException)
+ STD_EXCEPTION(0x1d00, InstructionBreakpoint, DebugException)
+ STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException)
+ STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException)
+
+
+ .globl _end_of_vectors
+_end_of_vectors:
+
+
+ . = 0x2000
+
+/*
+ * This code finishes saving the registers to the exception frame
+ * and jumps to the appropriate handler for the exception.
+ * Register r21 is pointer into trap frame, r1 has new stack pointer.
+ */
+ .globl transfer_to_handler
+transfer_to_handler:
+ stw r22,_NIP(r21)
+ lis r22,MSR_POW at h
+ andc r23,r23,r22
+ stw r23,_MSR(r21)
+ SAVE_GPR(7, r21)
+ SAVE_4GPRS(8, r21)
+ SAVE_8GPRS(12, r21)
+ SAVE_8GPRS(24, r21)
+ mflr r23
+ andi. r24,r23,0x3f00 /* get vector offset */
+ stw r24,TRAP(r21)
+ li r22,0
+ stw r22,RESULT(r21)
+ mtspr SPRG2,r22 /* r1 is now kernel sp */
+ lwz r24,0(r23) /* virtual address of handler */
+ lwz r23,4(r23) /* where to go when done */
+ mtspr SRR0,r24
+ mtspr SRR1,r20
+ mtlr r23
+ SYNC
+ rfi /* jump to handler, enable MMU */
+
+int_return:
+ mfmsr r28 /* Disable interrupts */
+ li r4,0
+ ori r4,r4,MSR_EE
+ andc r28,r28,r4
+ SYNC /* Some chip revs need this... */
+ mtmsr r28
+ SYNC
+ lwz r2,_CTR(r1)
+ lwz r0,_LINK(r1)
+ mtctr r2
+ mtlr r0
+ lwz r2,_XER(r1)
+ lwz r0,_CCR(r1)
+ mtspr XER,r2
+ mtcrf 0xFF,r0
+ REST_10GPRS(3, r1)
+ REST_10GPRS(13, r1)
+ REST_8GPRS(23, r1)
+ REST_GPR(31, r1)
+ lwz r2,_NIP(r1) /* Restore environment */
+ lwz r0,_MSR(r1)
+ mtspr SRR0,r2
+ mtspr SRR1,r0
+ lwz r0,GPR0(r1)
+ lwz r2,GPR2(r1)
+ lwz r1,GPR1(r1)
+ SYNC
+ rfi
+
+
+/*
+ * unsigned int get_immr (unsigned int mask)
+ *
+ * return (mask ? (IMMR & mask) : IMMR);
+ */
+ .globl get_immr
+get_immr:
+ mr r4,r3 /* save mask */
+ mfspr r3, IMMR /* IMMR */
+ cmpwi 0,r4,0 /* mask != 0 ? */
+ beq 4f
+ and r3,r3,r4 /* IMMR & mask */
+4:
+ blr
+
+ .globl get_pvr
+get_pvr:
+ mfspr r3, PVR
+ blr
+
+
+/*------------------------------------------------------------------------------*/
+
+/*
+ * void relocate_code (addr_sp, gd, addr_moni)
+ *
+ * This "function" does not return, instead it continues in RAM
+ * after relocating the monitor code.
+ *
+ * r3 = dest
+ * r4 = src
+ * r5 = length in bytes
+ * r6 = cachelinesize
+ */
+ .globl relocate_code
+relocate_code:
+ mr r1, r3 /* Set new stack pointer in SRAM */
+ mr r9, r4 /* Save copy of global data pointer in SRAM */
+ mr r10, r5 /* Save copy of monitor destination Address in SRAM */
+
+ GET_GOT
+ mr r3, r5 /* Destination Address */
+ lis r4, CONFIG_SYS_MONITOR_BASE at h /* Source Address */
+ ori r4, r4, CONFIG_SYS_MONITOR_BASE at l
+ lwz r5, GOT(__init_end)
+ sub r5, r5, r4
+
+ /*
+ * Fix GOT pointer:
+ *
+ * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
+ *
+ * Offset:
+ */
+ sub r15, r10, r4
+
+ /* First our own GOT */
+ add r12, r12, r15
+ /* the the one used by the C code */
+ add r30, r30, r15
+
+ /*
+ * Now relocate code
+ */
+
+ cmplw cr1,r3,r4
+ addi r0,r5,3
+ srwi. r0,r0,2
+ beq cr1,4f /* In place copy is not necessary */
+ beq 4f /* Protect against 0 count */
+ mtctr r0
+ bge cr1,2f
+
+ la r8,-4(r4)
+ la r7,-4(r3)
+1: lwzu r0,4(r8)
+ stwu r0,4(r7)
+ bdnz 1b
+ b 4f
+
+2: slwi r0,r0,2
+ add r8,r4,r0
+ add r7,r3,r0
+3: lwzu r0,-4(r8)
+ stwu r0,-4(r7)
+ bdnz 3b
+
+4: sync
+ isync
+
+/*
+ * We are done. Do not return, instead branch to second part of board
+ * initialization, now running from RAM.
+ */
+
+ addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
+ mtlr r0
+ blr
+
+in_ram:
+
+ /*
+ * Relocation Function, r12 point to got2+0x8000
+ *
+ * Adjust got2 pointers, no need to check for 0, this code
+ * already puts a few entries in the table.
+ */
+ li r0,__got2_entries at sectoff@l
+ la r3,GOT(_GOT2_TABLE_)
+ lwz r11,GOT(_GOT2_TABLE_)
+ mtctr r0
+ sub r11,r3,r11
+ addi r3,r3,-4
+1: lwzu r0,4(r3)
+ cmpwi r0,0
+ beq- 2f
+ add r0,r0,r11
+ stw r0,0(r3)
+2: bdnz 1b
+
+ /*
+ * Now adjust the fixups and the pointers to the fixups
+ * in case we need to move ourselves again.
+ */
+ li r0,__fixup_entries at sectoff@l
+ lwz r3,GOT(_FIXUP_TABLE_)
+ cmpwi r0,0
+ mtctr r0
+ addi r3,r3,-4
+ beq 4f
+3: lwzu r4,4(r3)
+ lwzux r0,r4,r11
+ cmpwi r0,0
+ add r0,r0,r11
+ stw r4,0(r3)
+ beq- 5f
+ stw r0,0(r4)
+5: bdnz 3b
+4:
+clear_bss:
+ /*
+ * Now clear BSS segment
+ */
+ lwz r3,GOT(__bss_start)
+ lwz r4,GOT(__bss_end)
+ cmplw 0, r3, r4
+ beq 6f
+
+ li r0, 0
+5:
+ stw r0, 0(r3)
+ addi r3, r3, 4
+ cmplw 0, r3, r4
+ bne 5b
+6:
+
+ mr r3, r9 /* Global Data pointer */
+ mr r4, r10 /* Destination Address */
+ bl board_init_r
+
+ /*
+ * Copy exception vector code to low memory
+ *
+ * r3: dest_addr
+ * r7: source address, r8: end address, r9: target address
+ */
+ .globl trap_init
+trap_init:
+ mflr r4 /* save link register */
+ GET_GOT
+ lwz r7, GOT(_start)
+ lwz r8, GOT(_end_of_vectors)
+
+ li r9, 0x100 /* reset vector always at 0x100 */
+
+ cmplw 0, r7, r8
+ bgelr /* return if r7>=r8 - just in case */
+1:
+ lwz r0, 0(r7)
+ stw r0, 0(r9)
+ addi r7, r7, 4
+ addi r9, r9, 4
+ cmplw 0, r7, r8
+ bne 1b
+
+ /*
+ * relocate `hdlr' and `int_return' entries
+ */
+ li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
+ li r8, Alignment - _start + EXC_OFF_SYS_RESET
+2:
+ bl trap_reloc
+ addi r7, r7, 0x100 /* next exception vector */
+ cmplw 0, r7, r8
+ blt 2b
+
+ li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
+ bl trap_reloc
+
+ li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
+ bl trap_reloc
+
+ li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
+ li r8, SystemCall - _start + EXC_OFF_SYS_RESET
+3:
+ bl trap_reloc
+ addi r7, r7, 0x100 /* next exception vector */
+ cmplw 0, r7, r8
+ blt 3b
+
+ li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
+ li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
+4:
+ bl trap_reloc
+ addi r7, r7, 0x100 /* next exception vector */
+ cmplw 0, r7, r8
+ blt 4b
+
+ mtlr r4 /* restore link register */
+ blr
+
+#if defined(CONFIG_PATI)
+/* Program the PLL */
+pll_prog_code_start:
+ lis r4, (CONFIG_SYS_IMMR + 0x002fc384)@h
+ ori r4, r4, (CONFIG_SYS_IMMR + 0x002fc384)@l
+ lis r3, (0x55ccaa33)@h
+ ori r3, r3, (0x55ccaa33)@l
+ stw r3, 0(r4)
+ lis r4, (CONFIG_SYS_IMMR + 0x002fc284)@h
+ ori r4, r4, (CONFIG_SYS_IMMR + 0x002fc284)@l
+ lis r3, CONFIG_SYS_PLPRCR at h
+ ori r3, r3, CONFIG_SYS_PLPRCR at l
+ stw r3, 0(r4)
+ addis r3,0,0x0
+ ori r3,r3,0xA000
+ mtctr r3
+..spinlp:
+ bdnz ..spinlp /* spin loop */
+ blr
+pll_prog_code_end:
+ nop
+ blr
+#endif
diff --git a/arch/powerpc/cpu/mpc5xx/traps.c b/arch/powerpc/cpu/mpc5xx/traps.c
new file mode 100644
index 0000000000..6f31d81493
--- /dev/null
+++ b/arch/powerpc/cpu/mpc5xx/traps.c
@@ -0,0 +1,211 @@
+/*
+ * linux/arch/powerpc/kernel/traps.c
+ *
+ * Copyright (C) 1995-1996 Gary Thomas (gdt at linuxppc.org)
+ *
+ * Modified by Cort Dougan (cort at cs.nmt.edu)
+ * and Paul Mackerras (paulus at cs.anu.edu.au)
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * This file handles the architecture-dependent parts of hardware exceptions
+ */
+
+#include <common.h>
+#include <command.h>
+#include <kgdb.h>
+#include <asm/processor.h>
+
+#if defined(CONFIG_CMD_BEDBUG)
+extern void do_bedbug_breakpoint(struct pt_regs *);
+#endif
+
+/* Returns 0 if exception not found and fixup otherwise. */
+extern unsigned long search_exception_table(unsigned long);
+
+/* THIS NEEDS CHANGING to use the board info structure.
+*/
+#define END_OF_MEM 0x0001000
+
+
+/*
+ * Print stack backtrace
+ */
+static void print_backtrace(unsigned long *sp)
+{
+ int cnt = 0;
+ unsigned long i;
+
+ printf("Call backtrace: ");
+ while (sp) {
+ if ((uint)sp > END_OF_MEM)
+ break;
+
+ i = sp[1];
+ if (cnt++ % 7 == 0)
+ printf("\n");
+ printf("%08lX ", i);
+ if (cnt > 32) break;
+ sp = (unsigned long *)*sp;
+ }
+ printf("\n");
+}
+
+/*
+ * Print current registers
+ */
+void show_regs(struct pt_regs *regs)
+{
+ int i;
+ printf("NIP: %08lX XER: %08lX LR: %08lX REGS: %p TRAP: %04lx DAR: %08lX\n",
+ regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar);
+ printf("MSR: %08lx EE: %01x PR: %01x FP: %01x ME: %01x IR/DR: %01x%01x\n",
+ regs->msr, regs->msr&MSR_EE ? 1 : 0, regs->msr&MSR_PR ? 1 : 0,
+ regs->msr & MSR_FP ? 1 : 0,regs->msr&MSR_ME ? 1 : 0,
+ regs->msr&MSR_IR ? 1 : 0,
+ regs->msr&MSR_DR ? 1 : 0);
+
+ printf("\n");
+ for (i = 0; i < 32; i++) {
+ if ((i % 8) == 0)
+ {
+ printf("GPR%02d: ", i);
+ }
+
+ printf("%08lX ", regs->gpr[i]);
+ if ((i % 8) == 7)
+ {
+ printf("\n");
+ }
+ }
+}
+
+
+/*
+ * General exception handler routine
+ */
+static void _exception(int signr, struct pt_regs *regs)
+{
+ show_regs(regs);
+ print_backtrace((unsigned long *)regs->gpr[1]);
+ panic("Exception in kernel pc %lx signal %d",regs->nip,signr);
+}
+
+/*
+ * Machine check exception handler routine
+ */
+void MachineCheckException(struct pt_regs *regs)
+{
+ unsigned long fixup;
+
+ /* Probing PCI using config cycles cause this exception
+ * when a device is not present. Catch it and return to
+ * the PCI exception handler.
+ */
+ if ((fixup = search_exception_table(regs->nip)) != 0) {
+ regs->nip = fixup;
+ return;
+ }
+
+#if defined(CONFIG_CMD_KGDB)
+ if (debugger_exception_handler && (*debugger_exception_handler)(regs))
+ return;
+#endif
+
+ printf("Machine check in kernel mode.\n");
+ printf("Caused by (from msr): ");
+ printf("regs %p ",regs);
+ switch( regs->msr & 0x000F0000) {
+ case (0x80000000>>12):
+ printf("Machine check signal\n");
+ break;
+ case (0x80000000>>13):
+ printf("Transfer error ack signal\n");
+ break;
+ case (0x80000000>>14):
+ printf("Data parity signal\n");
+ break;
+ case (0x80000000>>15):
+ printf("Address parity signal\n");
+ break;
+ default:
+ printf("Unknown values in msr\n");
+ }
+ show_regs(regs);
+ print_backtrace((unsigned long *)regs->gpr[1]);
+ panic("machine check");
+}
+
+/*
+ * Alignment exception handler routine
+ */
+void AlignmentException(struct pt_regs *regs)
+{
+#if defined(CONFIG_CMD_KGDB)
+ if (debugger_exception_handler && (*debugger_exception_handler)(regs))
+ return;
+#endif
+ show_regs(regs);
+ print_backtrace((unsigned long *)regs->gpr[1]);
+ panic("Alignment Exception");
+}
+
+/*
+ * Program check exception handler routine
+ */
+void ProgramCheckException(struct pt_regs *regs)
+{
+#if defined(CONFIG_CMD_KGDB)
+ if (debugger_exception_handler && (*debugger_exception_handler)(regs))
+ return;
+#endif
+ show_regs(regs);
+ print_backtrace((unsigned long *)regs->gpr[1]);
+ panic("Program Check Exception");
+}
+
+/*
+ * Software emulation exception handler routine
+ */
+void SoftEmuException(struct pt_regs *regs)
+{
+#if defined(CONFIG_CMD_KGDB)
+ if (debugger_exception_handler && (*debugger_exception_handler)(regs))
+ return;
+#endif
+ show_regs(regs);
+ print_backtrace((unsigned long *)regs->gpr[1]);
+ panic("Software Emulation Exception");
+}
+
+
+/*
+ * Unknown exception handler routine
+ */
+void UnknownException(struct pt_regs *regs)
+{
+#if defined(CONFIG_CMD_KGDB)
+ if (debugger_exception_handler && (*debugger_exception_handler)(regs))
+ return;
+#endif
+ printf("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
+ regs->nip, regs->msr, regs->trap);
+ _exception(0, regs);
+}
+
+/*
+ * Debug exception handler routine
+ */
+void DebugException(struct pt_regs *regs)
+{
+ printf("Debugger trap at @ %lx\n", regs->nip );
+ show_regs(regs);
+#if defined(CONFIG_CMD_BEDBUG)
+ do_bedbug_breakpoint( regs );
+#endif
+}
diff --git a/arch/powerpc/cpu/mpc5xx/u-boot.lds b/arch/powerpc/cpu/mpc5xx/u-boot.lds
new file mode 100644
index 0000000000..6a5357124d
--- /dev/null
+++ b/arch/powerpc/cpu/mpc5xx/u-boot.lds
@@ -0,0 +1,86 @@
+/*
+ * (C) Copyright 2001-2010 Wolfgang Denk, DENX Software Engineering, wd at denx.de
+ * (C) Copyright 2003 Martin Winistoerfer, martinwinistoerfer at gmx.ch
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+OUTPUT_ARCH(powerpc)
+
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .text :
+ {
+ arch/powerpc/cpu/mpc5xx/start.o (.text*)
+
+ *(.text*)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+ }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ _GOT2_TABLE_ = .;
+ KEEP(*(.got2))
+ KEEP(*(.got))
+ _FIXUP_TABLE_ = .;
+ KEEP(*(.fixup))
+ }
+ __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data*)
+ *(.sdata*)
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ KEEP(*(SORT(.u_boot_list*)));
+ }
+
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss (NOLOAD) :
+ {
+ *(.bss*)
+ *(.sbss*)
+ *(COMMON)
+ . = ALIGN(4);
+ }
+
+ __bss_end = . ;
+ PROVIDE (end = .);
+ . = env_start;
+ .ppcenv :
+ {
+ common/env_embedded.o (.ppcenv)
+ }
+}
diff --git a/arch/powerpc/include/asm/5xx_immap.h b/arch/powerpc/include/asm/5xx_immap.h
new file mode 100644
index 0000000000..0a333c2ad6
--- /dev/null
+++ b/arch/powerpc/include/asm/5xx_immap.h
@@ -0,0 +1,424 @@
+/*
+ * (C) Copyright 2003
+ * Martin Winistoerfer, martinwinistoerfer at gmx.ch.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * File: 5xx_immap.h
+ *
+ * Discription: MPC555 Internal Memory Map
+ *
+ */
+
+#ifndef __IMMAP_5XX__
+#define __IMMAP_5XX__
+
+/* System Configuration Registers.
+*/
+typedef struct sys_conf {
+ uint sc_siumcr;
+ uint sc_sypcr;
+ char res1[6];
+ ushort sc_swsr;
+ uint sc_sipend;
+ uint sc_simask;
+ uint sc_siel;
+ uint sc_sivec;
+ uint sc_tesr;
+ uint sc_sgpiodt1;
+ uint sc_sgpiodt2;
+ uint sc_sgpiocr;
+ uint sc_emcr;
+ uint sc_res1aa;
+ uint sc_res1ab;
+ uint sc_pdmcr;
+ char res3[192];
+} sysconf5xx_t;
+
+
+/* Memory Controller Registers.
+*/
+typedef struct mem_ctlr {
+ uint memc_br0;
+ uint memc_or0;
+ uint memc_br1;
+ uint memc_or1;
+ uint memc_br2;
+ uint memc_or2;
+ uint memc_br3;
+ uint memc_or3;
+ char res1[32];
+ uint memc_dmbr;
+ uint memc_dmor;
+ char res2[48];
+ ushort memc_mstat;
+ ushort memc_res4a;
+ char res3[132];
+} memctl5xx_t;
+
+/* System Integration Timers.
+*/
+typedef struct sys_int_timers {
+ ushort sit_tbscr;
+ char res1[2];
+ uint sit_tbref0;
+ uint sit_tbref1;
+ char res2[20];
+ ushort sit_rtcsc;
+ char res3[2];
+ uint sit_rtc;
+ uint sit_rtsec;
+ uint sit_rtcal;
+ char res4[16];
+ ushort sit_piscr;
+ char res5[2];
+ uint sit_pitc;
+ uint sit_pitr;
+ char res6[52];
+} sit5xx_t;
+
+/* Clocks and Reset
+*/
+typedef struct clk_and_reset {
+ uint car_sccr;
+ uint car_plprcr;
+ ushort car_rsr;
+ ushort car_res7a;
+ ushort car_colir;
+ ushort car_res7b;
+ ushort car_vsrmcr;
+ ushort car_res7c;
+ char res1[108];
+
+} car5xx_t;
+
+#define TBSCR_TBE ((ushort)0x0001)
+
+/* System Integration Timer Keys
+*/
+typedef struct sitk {
+ uint sitk_tbscrk;
+ uint sitk_tbref0k;
+ uint sitk_tbref1k;
+ uint sitk_tbk;
+ char res1[16];
+ uint sitk_rtcsck;
+ uint sitk_rtck;
+ uint sitk_rtseck;
+ uint sitk_rtcalk;
+ char res2[16];
+ uint sitk_piscrk;
+ uint sitk_pitck;
+ char res3[56];
+} sitk5xx_t;
+
+/* Clocks and Reset Keys.
+*/
+typedef struct cark {
+ uint cark_sccrk;
+ uint cark_plprcrk;
+ uint cark_rsrk;
+ char res1[1140];
+} cark8xx_t;
+
+/* The key to unlock registers maintained by keep-alive power.
+*/
+#define KAPWR_KEY ((unsigned int)0x55ccaa33)
+
+/* Flash Configuration
+*/
+typedef struct fl {
+ uint fl_cmfmcr;
+ uint fl_cmftst;
+ uint fl_cmfctl;
+ char res1[52];
+} fl5xx_t;
+
+/* Dpram Control
+*/
+typedef struct dprc {
+ ushort dprc_dptmcr;
+ ushort dprc_ramtst;
+ ushort dprc_rambar;
+ ushort dprc_misrh;
+ ushort dprc_misrl;
+ ushort dprc_miscnt;
+} dprc5xx_t;
+
+/* Time Processor Unit
+*/
+typedef struct tpu {
+ ushort tpu_tpumcr;
+ ushort tpu_tcr;
+ ushort tpu_dscr;
+ ushort tpu_dssr;
+ ushort tpu_ticr;
+ ushort tpu_cier;
+ ushort tpu_cfsr0;
+ ushort tpu_cfsr1;
+ ushort tpu_cfsr2;
+ ushort tpu_cfsr3;
+ ushort tpu_hsqr0;
+ ushort tpu_hsqr1;
+ ushort tpu_hsrr0;
+ ushort tpu_hsrr1;
+ ushort tpu_cpr0;
+ ushort tpu_cpr1;
+ ushort tpu_cisr;
+ ushort tpu_lr;
+ ushort tpu_sglr;
+ ushort tpu_dcnr;
+ ushort tpu_tpumcr2;
+ ushort tpu_tpumcr3;
+ ushort tpu_isdr;
+ ushort tpu_iscr;
+ char res1[208];
+ char tpu[16][16];
+ char res2[512];
+} tpu5xx_t;
+
+/* QADC
+*/
+typedef struct qadc {
+ ushort qadc_64mcr;
+ ushort qadc_64test;
+ ushort qadc_64int;
+ u_char qadc_portqa;
+ u_char qadc_portqb;
+ ushort qadc_ddrqa;
+ ushort qadc_qacr0;
+ ushort qadc_qacr1;
+ ushort qadc_qacr2;
+ ushort qadc_qasr0;
+ ushort qadc_qasr1;
+ char res1[492];
+ /* command convertion word table */
+ ushort qadc_ccw[64];
+ /* result word table, unsigned right justified */
+ ushort qadc_rjurr[64];
+ /* result word table, signed left justified */
+ ushort qadc_ljsrr[64];
+ /* result word table, unsigned left justified */
+ ushort qadc_ljurr[64];
+} qadc5xx_t;
+
+/* QSMCM
+*/
+typedef struct qsmcm {
+ ushort qsmcm_qsmcr;
+ ushort qsmcm_qtest;
+ ushort qsmcm_qdsci_il;
+ ushort qsmcm_qspi_il;
+ ushort qsmcm_scc1r0;
+ ushort qsmcm_scc1r1;
+ ushort qsmcm_sc1sr;
+ ushort qsmcm_sc1dr;
+ char res1[2];
+ char res2[2];
+ ushort qsmcm_portqs;
+ u_char qsmcm_pqspar;
+ u_char qsmcm_ddrqs;
+ ushort qsmcm_spcr0;
+ ushort qsmcm_spcr1;
+ ushort qsmcm_spcr2;
+ u_char qsmcm_spcr3;
+ u_char qsmcm_spsr;
+ ushort qsmcm_scc2r0;
+ ushort qsmcm_scc2r1;
+ ushort qsmcm_sc2sr;
+ ushort qsmcm_sc2dr;
+ ushort qsmcm_qsci1cr;
+ ushort qsmcm_qsci1sr;
+ ushort qsmcm_sctq[16];
+ ushort qsmcm_scrq[16];
+ char res3[212];
+ ushort qsmcm_recram[32];
+ ushort qsmcm_tranram[32];
+ u_char qsmcm_comdram[32];
+ char res[3616];
+} qsmcm5xx_t;
+
+
+/* MIOS
+*/
+
+typedef struct mios {
+ ushort mios_mpwmsm0perr; /* mpwmsm0 */
+ ushort mios_mpwmsm0pulr;
+ ushort mios_mpwmsm0cntr;
+ ushort mios_mpwmsm0scr;
+ ushort mios_mpwmsm1perr; /* mpwmsm1 */
+ ushort mios_mpwmsm1pulr;
+ ushort mios_mpwmsm1cntr;
+ ushort mios_mpwmsm1scr;
+ ushort mios_mpwmsm2perr; /* mpwmsm2 */
+ ushort mios_mpwmsm2pulr;
+ ushort mios_mpwmsm2cntr;
+ ushort mios_mpwmsm2scr;
+ ushort mios_mpwmsm3perr; /* mpwmsm3 */
+ ushort mios_mpwmsm3pulr;
+ ushort mios_mpwmsm3cntr;
+ ushort mios_mpwmsm3scr;
+ char res1[16];
+ ushort mios_mmcsm6cnt; /* mmcsm6 */
+ ushort mios_mmcsm6mlr;
+ ushort mios_mmcsm6scrd, mmcsm6scr;
+ char res2[32];
+ ushort mios_mdasm11ar; /* mdasm11 */
+ ushort mios_mdasm11br;
+ ushort mios_mdasm11scrd, mdasm11scr;
+ ushort mios_mdasm12ar; /* mdasm12 */
+ ushort mios_mdasm12br;
+ ushort mios_mdasm12scrd, mdasm12scr;
+ ushort mios_mdasm13ar; /* mdasm13 */
+ ushort mios_mdasm13br;
+ ushort mios_mdasm13scrd, mdasm13scr;
+ ushort mios_mdasm14ar; /* mdasm14 */
+ ushort mios_mdasm14br;
+ ushort mios_mdasm14scrd, mdasm14scr;
+ ushort mios_mdasm15ar; /* mdasm15 */
+ ushort mios_mdasm15br;
+ ushort mios_mdasm15scrd, mdasm15scr;
+ ushort mios_mpwmsm16perr; /* mpwmsm16 */
+ ushort mios_mpwmsm16pulr;
+ ushort mios_mpwmsm16cntr;
+ ushort mios_mpwmsm16scr;
+ ushort mios_mpwmsm17perr; /* mpwmsm17 */
+ ushort mios_mpwmsm17pulr;
+ ushort mios_mpwmsm17cntr;
+ ushort mios_mpwmsm17scr;
+ ushort mios_mpwmsm18perr; /* mpwmsm18 */
+ ushort mios_mpwmsm18pulr;
+ ushort mios_mpwmsm18cntr;
+ ushort mios_mpwmsm18scr;
+ ushort mios_mpwmsm19perr; /* mpwmsm19 */
+ ushort mios_mpwmsm19pulr;
+ ushort mios_mpwmsm19cntr;
+ ushort mios_mpwmsm19scr;
+ char res3[16];
+ ushort mios_mmcsm22cnt; /* mmcsm22 */
+ ushort mios_mmcsm22mlr;
+ ushort mios_mmcsm22scrd, mmcsm22scr;
+ char res4[32];
+ ushort mios_mdasm27ar; /* mdasm27 */
+ ushort mios_mdasm27br;
+ ushort mios_mdasm27scrd, mdasm27scr;
+ ushort mios_mdasm28ar; /*mdasm28 */
+ ushort mios_mdasm28br;
+ ushort mios_mdasm28scrd, mdasm28scr;
+ ushort mios_mdasm29ar; /* mdasm29 */
+ ushort mios_mdasm29br;
+ ushort mios_mdasm29scrd, mdasm29scr;
+ ushort mios_mdasm30ar; /* mdasm30 */
+ ushort mios_mdasm30br;
+ ushort mios_mdasm30scrd, mdasm30scr;
+ ushort mios_mdasm31ar; /* mdasm31 */
+ ushort mios_mdasm31br;
+ ushort mios_mdasm31scrd, mdasm31scr;
+ ushort mios_mpiosm32dr;
+ ushort mios_mpiosm32ddr;
+ char res5[1788];
+ ushort mios_mios1tpcr;
+ char mios_res13[2];
+ ushort mios_mios1vnr;
+ ushort mios_mios1mcr;
+ char res6[12];
+ ushort mios_res42z;
+ ushort mios_mcpsmscr;
+ char res7[1000];
+ ushort mios_mios1sr0;
+ char res12[2];
+ ushort mios_mios1er0;
+ ushort mios_mios1rpr0;
+ char res8[40];
+ ushort mios_mios1lvl0;
+ char res9[14];
+ ushort mios_mios1sr1;
+ char res10[2];
+ ushort mios_mios1er1;
+ ushort mios_mios1rpr1;
+ char res11[40];
+ ushort mios_mios1lvl1;
+ char res13[1038];
+} mios5xx_t;
+
+/* Toucan Module
+*/
+typedef struct tcan {
+ ushort tcan_tcnmcr;
+ ushort tcan_cantcr;
+ ushort tcan_canicr;
+ u_char tcan_canctrl0;
+ u_char tcan_canctrl1;
+ u_char tcan_presdiv;
+ u_char tcan_canctrl2;
+ ushort tcan_timer;
+ char res1[4];
+ ushort tcan_rxgmskhi;
+ ushort tcan_rxgmsklo;
+ ushort tcan_rx14mskhi;
+ ushort tcan_rx14msklo;
+ ushort tcan_rx15mskhi;
+ ushort tcan_rx15msklo;
+ char res2[4];
+ ushort tcan_estat;
+ ushort tcan_imask;
+ ushort tcan_iflag;
+ u_char tcan_rxectr;
+ u_char tcan_txectr;
+ char res3[88];
+ struct {
+ ushort scr;
+ ushort id_high;
+ ushort id_low;
+ u_char data[8];
+ char res4[2];
+ } tcan_mbuff[16];
+ char res5[640];
+} tcan5xx_t;
+
+/* UIMB
+*/
+typedef struct uimb {
+ uint uimb_umcr;
+ char res1[12];
+ uint uimb_utstcreg;
+ char res2[12];
+ uint uimb_uipend;
+} uimb5xx_t;
+
+
+/* Internal Memory Map MPC555
+*/
+typedef struct immap {
+ char res1[262144]; /* CMF Flash A 256 Kbytes */
+ char res2[196608]; /* CMF Flash B 192 Kbytes */
+ char res3[2670592]; /* Reserved for Flash */
+ sysconf5xx_t im_siu_conf; /* SIU Configuration */
+ memctl5xx_t im_memctl; /* Memory Controller */
+ sit5xx_t im_sit; /* System Integration Timers */
+ car5xx_t im_clkrst; /* Clocks and Reset */
+ sitk5xx_t im_sitk; /* System Integration Timer Keys*/
+ cark8xx_t im_clkrstk; /* Clocks and Resert Keys */
+ fl5xx_t im_fla; /* Flash Module A */
+ fl5xx_t im_flb; /* Flash Module B */
+ char res4[14208]; /* Reserved for SIU */
+ dprc5xx_t im_dprc; /* Dpram Control Register */
+ char res5[8180]; /* Reserved */
+ char dptram[6144]; /* Dptram */
+ char res6[2048]; /* Reserved */
+ tpu5xx_t im_tpua; /* Time Proessing Unit A */
+ tpu5xx_t im_tpub; /* Time Processing Unit B */
+ qadc5xx_t im_qadca; /* QADC A */
+ qadc5xx_t im_qadcb; /* QADC B */
+ qsmcm5xx_t im_qsmcm; /* SCI and SPI */
+ mios5xx_t im_mios; /* MIOS */
+ tcan5xx_t im_tcana; /* Toucan A */
+ tcan5xx_t im_tcanb; /* Toucan B */
+ char res7[1792]; /* Reserved */
+ uimb5xx_t im_uimb; /* UIMB */
+} immap_t;
+
+#endif /* __IMMAP_5XX__ */
diff --git a/arch/powerpc/include/asm/ppc.h b/arch/powerpc/include/asm/ppc.h
index f5e9334cc7..f23ed3e1b4 100644
--- a/arch/powerpc/include/asm/ppc.h
+++ b/arch/powerpc/include/asm/ppc.h
@@ -13,7 +13,9 @@
#ifndef __ASSEMBLY__
-#if defined(CONFIG_MPC5xxx)
+#if defined(CONFIG_5xx)
+#include <asm/5xx_immap.h>
+#elif defined(CONFIG_MPC5xxx)
#include <mpc5xxx.h>
#elif defined(CONFIG_MPC512X)
#include <asm/immap_512x.h>
@@ -43,6 +45,9 @@
#include <asm/arch/immap_lsch2.h>
#endif
+#if defined(CONFIG_5xx)
+uint get_immr(uint);
+#endif
#if defined(CONFIG_MPC5xxx)
uint get_svr(void);
#endif
diff --git a/arch/powerpc/include/asm/status_led.h b/arch/powerpc/include/asm/status_led.h
new file mode 100644
index 0000000000..2767c05297
--- /dev/null
+++ b/arch/powerpc/include/asm/status_led.h
@@ -0,0 +1,73 @@
+/*
+ * asm/status_led.h
+ *
+ * MPC8xx/MPC8260/MPC5xx based status led support functions
+ */
+
+#ifndef __ASM_STATUS_LED_H__
+#define __ASM_STATUS_LED_H__
+
+/* if not overridden */
+#ifndef CONFIG_LED_STATUS_BOARD_SPECIFIC
+# if defined(CONFIG_5xx)
+# include <mpc5xx.h>
+# else
+# error CPU specific Status LED header file missing.
+#endif
+
+/* led_id_t is unsigned long mask */
+typedef unsigned long led_id_t;
+
+static inline void __led_init (led_id_t mask, int state)
+{
+ volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
+
+#ifdef STATUS_LED_PAR
+ immr->STATUS_LED_PAR &= ~mask;
+#endif
+#ifdef STATUS_LED_ODR
+ immr->STATUS_LED_ODR &= ~mask;
+#endif
+
+#if (STATUS_LED_ACTIVE == 0)
+ if (state == CONFIG_LED_STATUS_ON)
+ immr->STATUS_LED_DAT &= ~mask;
+ else
+ immr->STATUS_LED_DAT |= mask;
+#else
+ if (state == CONFIG_LED_STATUS_ON)
+ immr->STATUS_LED_DAT |= mask;
+ else
+ immr->STATUS_LED_DAT &= ~mask;
+#endif
+#ifdef STATUS_LED_DIR
+ immr->STATUS_LED_DIR |= mask;
+#endif
+}
+
+static inline void __led_toggle (led_id_t mask)
+{
+ ((immap_t *) CONFIG_SYS_IMMR)->STATUS_LED_DAT ^= mask;
+}
+
+static inline void __led_set (led_id_t mask, int state)
+{
+ volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
+
+#if (STATUS_LED_ACTIVE == 0)
+ if (state == CONFIG_LED_STATUS_ON)
+ immr->STATUS_LED_DAT &= ~mask;
+ else
+ immr->STATUS_LED_DAT |= mask;
+#else
+ if (state == CONFIG_LED_STATUS_ON)
+ immr->STATUS_LED_DAT |= mask;
+ else
+ immr->STATUS_LED_DAT &= ~mask;
+#endif
+
+}
+
+#endif
+
+#endif /* __ASM_STATUS_LED_H__ */
diff --git a/arch/powerpc/lib/time.c b/arch/powerpc/lib/time.c
index 3a5ad4d8d2..c1a0a69a51 100644
--- a/arch/powerpc/lib/time.c
+++ b/arch/powerpc/lib/time.c
@@ -64,10 +64,21 @@ int timer_init(void)
{
unsigned long temp;
+#if defined(CONFIG_5xx)
+ volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+
+ /* unlock */
+ immap->im_sitk.sitk_tbk = KAPWR_KEY;
+#endif
+
/* reset */
asm volatile("li %0,0 ; mttbu %0 ; mttbl %0;"
: "=&r"(temp) );
+#if defined(CONFIG_5xx)
+ /* enable */
+ immap->im_sit.sit_tbscr |= TBSCR_TBE;
+#endif
return (0);
}
/* ------------------------------------------------------------------------- */
diff --git a/board/mpl/common/common_util.c b/board/mpl/common/common_util.c
index 31636b30ee..5ea5a5187b 100644
--- a/board/mpl/common/common_util.c
+++ b/board/mpl/common/common_util.c
@@ -28,6 +28,10 @@
DECLARE_GLOBAL_DATA_PTR;
+#if defined(CONFIG_PATI)
+#define FIRM_START 0xFFF00000
+#endif
+
extern int mem_test(ulong start, ulong ramsize, int quiet);
#define I2C_BACKUP_ADDR 0x7C00 /* 0x200 bytes for backup */
@@ -185,8 +189,11 @@ mpl_prg(uchar *src, ulong size)
ulong start;
flash_info_t *info = &flash_info[0];
int i, rc;
-#if defined(CONFIG_PIP405) || defined(CONFIG_TARGET_MIP405) || \
- defined(CONFIG_TARGET_MIP405T)
+#if defined(CONFIG_PATI)
+ int start_sect;
+#endif
+#if defined(CONFIG_PIP405) || defined(CONFIG_TARGET_MIP405) \
+ || defined(CONFIG_TARGET_MIP405T) || defined(CONFIG_PATI)
char *copystr = (char *)src;
ulong *magic = (ulong *)src;
@@ -212,6 +219,7 @@ mpl_prg(uchar *src, ulong size)
printf("Wrong Firmware Image: %s\n", ©str[i]);
return -1;
}
+#if !defined(CONFIG_PATI)
start = 0 - size;
/* unprotect sectors used by u-boot */
@@ -233,6 +241,38 @@ mpl_prg(uchar *src, ulong size)
flash_perror(rc);
return (1);
}
+
+#else /* #if !defined(CONFIG_PATI) */
+ start = FIRM_START;
+ start_sect = -1;
+
+ /* search start sector */
+ for (i = info->sector_count-1; i > 0; i--)
+ if (start >= info->start[i])
+ break;
+
+ start_sect = i;
+
+ for (i = info->sector_count-1; i > 0; i--)
+ if ((start + size) >= info->start[i])
+ break;
+
+ /* unprotect sectors used by u-boot */
+ flash_protect(FLAG_PROTECT_CLEAR,
+ start,
+ start + size,
+ info);
+
+ /* now erase flash */
+ printf ("Erasing at %lx to %lx (sector %d to %d) (%lx to %lx)\n",
+ start, start + size, start_sect, i,
+ info->start[start_sect], info->start[i]);
+ if ((rc = flash_erase (info, start_sect, i)) != 0) {
+ puts ("ERROR ");
+ flash_perror (rc);
+ return (1);
+ }
+#endif /* defined(CONFIG_PATI) */
#endif
printf("flash erased, programming from 0x%lx 0x%lx Bytes\n",
(ulong)src, size);
@@ -340,6 +380,7 @@ mpl_prg_image(uchar *ld_addr)
return(rc);
}
+#if !defined(CONFIG_PATI)
void get_backup_values(backup_t *buf)
{
i2c_read(CONFIG_SYS_DEF_EEPROM_ADDR, I2C_BACKUP_ADDR,2,(void *)buf,sizeof(backup_t));
@@ -500,13 +541,17 @@ void check_env(void)
}
}
+#endif /* #if !defined(CONFIG_PATI) */
+
int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
ulong ld_addr;
int result;
+#if !defined(CONFIG_PATI)
ulong size = IMAGE_SIZE;
ulong src = MULTI_PURPOSE_SOCKET_ADDR;
backup_t back;
+#endif
if (strcmp(argv[1], "flash") == 0)
{
@@ -542,12 +587,15 @@ int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
result=mpl_prg_image((uchar *)ld_addr);
return result;
}
+#if !defined(CONFIG_PATI)
if (strcmp(argv[2], "mps") == 0) {
puts("\nupdating bootloader image from MPS\n");
result=mpl_prg((uchar *)src,size);
return result;
}
+#endif /* #if !defined(CONFIG_PATI) */
}
+#if !defined(CONFIG_PATI)
if (strcmp(argv[1], "clearenvvalues") == 0)
{
if (strcmp(argv[2], "yes") == 0)
@@ -570,6 +618,7 @@ int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
set_backup_values(1);
return 0;
}
+#endif
return cmd_usage(cmdtp);
}
diff --git a/board/mpl/pati/Kconfig b/board/mpl/pati/Kconfig
new file mode 100644
index 0000000000..0eeaf7096b
--- /dev/null
+++ b/board/mpl/pati/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_PATI
+
+config SYS_BOARD
+ default "pati"
+
+config SYS_VENDOR
+ default "mpl"
+
+config SYS_CONFIG_NAME
+ default "PATI"
+
+config ISO_STRING
+ string
+ default "MEV-10084-001"
+endif
diff --git a/board/mpl/pati/MAINTAINERS b/board/mpl/pati/MAINTAINERS
new file mode 100644
index 0000000000..19ad05d274
--- /dev/null
+++ b/board/mpl/pati/MAINTAINERS
@@ -0,0 +1,6 @@
+PATI BOARD
+#M: -
+S: Maintained
+F: board/mpl/pati/
+F: include/configs/PATI.h
+F: configs/PATI_defconfig
diff --git a/board/mpl/pati/Makefile b/board/mpl/pati/Makefile
new file mode 100644
index 0000000000..9822082612
--- /dev/null
+++ b/board/mpl/pati/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := pati.o cmd_pati.o \
+ ../common/common_util.o
diff --git a/board/mpl/pati/cmd_pati.c b/board/mpl/pati/cmd_pati.c
new file mode 100644
index 0000000000..fcae5e0de6
--- /dev/null
+++ b/board/mpl/pati/cmd_pati.c
@@ -0,0 +1,433 @@
+/*
+ * (C) Copyright 2001
+ * Denis Peter, MPL AG Switzerland, d.peter at mpl.ch
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Adapted for PATI
+ */
+
+#include <common.h>
+#include <command.h>
+#define PLX9056_LOC
+#include "plx9056.h"
+#include "pati.h"
+#include "pci_eeprom.h"
+
+extern void show_pld_regs(void);
+extern int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+
+extern void user_led0(int led_on);
+extern void user_led1(int led_on);
+
+/* ------------------------------------------------------------------------- */
+#if defined(CONFIG_SYS_PCI_CON_DEVICE)
+extern void pci_con_disc(void);
+extern void pci_con_connect(void);
+#endif
+
+/******************************************************************************
+ * Eeprom Support
+ ******************************************************************************/
+unsigned long get32(unsigned long addr)
+{
+ unsigned long *p=(unsigned long *)addr;
+ return *p;
+}
+
+void set32(unsigned long addr,unsigned long data)
+{
+ unsigned long *p=(unsigned long *)addr;
+ *p=data;
+}
+
+#define PCICFG_GET_REG(x) (get32((x) + PCI_CONFIG_BASE))
+#define PCICFG_SET_REG(x,y) (set32((x) + PCI_CONFIG_BASE,(y)))
+
+
+/******************************************************************************
+ * reload_pci_eeprom
+ ******************************************************************************/
+
+static void reload_pci_eeprom(void)
+{
+ unsigned long reg;
+ /* Set Bit 29 and clear it again */
+ reg=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT);
+ udelay(1);
+ /* set it*/
+ reg|=(1<<29);
+ PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg);
+ /* EECLK @ 33MHz = 125kHz
+ * -> extra long load = 32 * 16bit = 512Bit @ 125kHz = 4.1msec
+ * use 20msec
+ */
+ udelay(20000); /* wait 20ms */
+ reg &= ~(1<<29); /* set it low */
+ PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg);
+ udelay(1); /* wait some time */
+}
+
+/******************************************************************************
+ * clock_pci_eeprom
+ ******************************************************************************/
+
+static void clock_pci_eeprom(void)
+{
+ unsigned long reg;
+ /* clock is low, data is valid */
+ reg=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT);
+ udelay(1);
+ /* set clck high */
+ reg|=(1<<24);
+ PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg);
+ udelay(1); /* wait some time */
+ reg &= ~(1<<24); /* set clock low */
+ PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg);
+ udelay(1); /* wait some time */
+}
+
+/******************************************************************************
+ * send_pci_eeprom_cmd
+ ******************************************************************************/
+static void send_pci_eeprom_cmd(unsigned long cmd, unsigned char len)
+{
+ unsigned long reg;
+ int i;
+ reg=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT);
+ /* Clear all EEPROM bits */
+ reg &= ~(0xF << 24);
+ /* Toggle EEPROM's Chip select to get it out of Shift Register Mode */
+ PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg);
+ udelay(1); /* wait some time */
+ /* Enable EEPROM Chip Select */
+ reg |= (1 << 25);
+ PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg);
+ /* Send EEPROM command - one bit at a time */
+ for (i = (int)(len-1); i >= 0; i--) {
+ /* Check if current bit is 0 or 1 */
+ if (cmd & (1 << i))
+ PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,(reg | (1<<26)));
+ else
+ PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg);
+ clock_pci_eeprom();
+ }
+}
+
+/******************************************************************************
+ * write_pci_eeprom_offs
+ ******************************************************************************/
+static void write_pci_eeprom_offs(unsigned short offset, unsigned short value)
+{
+ unsigned long reg;
+ int bitpos, cmdshft, cmdlen, timeout;
+ /* we're using the Eeprom 93CS66 */
+ cmdshft = 2;
+ cmdlen = EE66_CMD_LEN;
+ /* Send Write_Enable command to EEPROM */
+ send_pci_eeprom_cmd((EE_WREN << cmdshft),cmdlen);
+ /* Send EEPROM Write command and offset to EEPROM */
+ send_pci_eeprom_cmd((EE_WRITE << cmdshft) | (offset / 2),cmdlen);
+ reg=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT);
+ /* Clear all EEPROM bits */
+ reg &= ~(0xF << 24);
+ /* Make sure EEDO Input is disabled for some PLX chips */
+ reg &= ~(1 << 31);
+ /* Enable EEPROM Chip Select */
+ reg |= (1 << 25);
+ /* Write 16-bit value to EEPROM - one bit at a time */
+ for (bitpos = 15; bitpos >= 0; bitpos--) {
+ /* Get bit value and shift into result */
+ if (value & (1 << bitpos))
+ PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,(reg | (1<<26)));
+ else
+ PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg );
+ clock_pci_eeprom();
+ } /* for */
+ /* Deselect Chip */
+ PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg & ~(1 << 25));
+ /* Re-select Chip */
+ PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg | (1 << 25));
+ /* A small delay is needed to let EEPROM complete */
+ timeout = 0;
+ do {
+ udelay(10);
+ reg=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT);
+ timeout++;
+ } while (((reg & (1 << 27)) == 0) && timeout < 20000);
+ /* Send Write_Disable command to EEPROM */
+ send_pci_eeprom_cmd((EE_WDS << cmdshft),cmdlen);
+ /* Clear Chip Select and all other EEPROM bits */
+ PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg & ~(0xF << 24));
+}
+
+
+/******************************************************************************
+ * read_pci_eeprom_offs
+ ******************************************************************************/
+static void read_pci_eeprom_offs(unsigned short offset, unsigned short *pvalue)
+{
+ unsigned long reg;
+ int bitpos, cmdshft, cmdlen;
+ /* we're using the Eeprom 93CS66 */
+ cmdshft = 2;
+ cmdlen = EE66_CMD_LEN;
+ /* Send EEPROM read command and offset to EEPROM */
+ send_pci_eeprom_cmd((EE_READ << cmdshft) | (offset / 2),cmdlen);
+ /* Set EEPROM write output bit */
+ reg=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT);
+ /* Set EEDO Input enable */
+ reg |= (1 << 31);
+ PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg | (1 << 26));
+ /* Get 16-bit value from EEPROM - one bit at a time */
+ for (bitpos = 0; bitpos < 16; bitpos++) {
+ clock_pci_eeprom();
+ udelay(10);
+ reg=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT);
+ /* Get bit value and shift into result */
+ if (reg & (1 << 27))
+ *pvalue = (unsigned short)((*pvalue << 1) | 1);
+ else
+ *pvalue = (unsigned short)(*pvalue << 1);
+ }
+ /* Clear EEDO Input enable */
+ reg &= ~(1 << 31);
+ /* Clear Chip Select and all other EEPROM bits */
+ PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg & ~(0xF << 24));
+}
+
+
+/******************************************************************************
+ * EEPROM read/writes
+******************************************************************************/
+
+#undef EEPROM_DBG
+static int pati_pci_eeprom_erase(void)
+{
+ int i;
+ printf("Erasing EEPROM ");
+ for( i=0; i < PATI_EEPROM_LAST_OFFSET; i+=2) {
+ write_pci_eeprom_offs(i,0xffff);
+ if((i%0x10))
+ printf(".");
+ }
+ printf("\nDone\n");
+ return 0;
+}
+
+static int pati_pci_eeprom_prg(void)
+{
+ int i;
+ i=0;
+ printf("Programming EEPROM ");
+ while(pati_eeprom[i].offset<0xffff) {
+ write_pci_eeprom_offs(pati_eeprom[i].offset,pati_eeprom[i].value);
+ #ifdef EEPROM_DBG
+ printf("0x%04X: 0x%04X\n",pati_eeprom[i].offset, pati_eeprom[i].value);
+ #else
+ if((i%0x10))
+ printf(".");
+ #endif
+ i++;
+ }
+ printf("\nDone\n");
+ return 0;
+}
+
+static int pati_pci_eeprom_write(unsigned short offset, unsigned long addr, unsigned short size)
+{
+ int i;
+ unsigned short value;
+ unsigned short *buffer =(unsigned short *)addr;
+ if((offset + size) > PATI_EEPROM_LAST_OFFSET) {
+ size = PATI_EEPROM_LAST_OFFSET - offset;
+ }
+ printf("Write To EEPROM from 0x%lX to 0x%X 0x%X words\n", addr, offset, size/2);
+ for( i = offset; i< (offset + size); i+=2) {
+ value = *buffer++;
+ write_pci_eeprom_offs(i,value);
+ #ifdef EEPROM_DBG
+ printf("0x%04X: 0x%04X\n",i, value);
+ #else
+ if((i%0x10))
+ printf(".");
+ #endif
+ }
+ printf("\nDone\n");
+ return 0;
+}
+
+static int pati_pci_eeprom_read(unsigned short offset, unsigned long addr, unsigned short size)
+{
+ int i;
+ unsigned short value = 0;
+ unsigned short *buffer =(unsigned short *)addr;
+ if((offset + size) > PATI_EEPROM_LAST_OFFSET) {
+ size = PATI_EEPROM_LAST_OFFSET - offset;
+ }
+ printf("Read from EEPROM from 0x%X to 0x%lX 0x%X words\n", offset, addr, size/2);
+ for( i = offset; i< (offset + size); i+=2) {
+ read_pci_eeprom_offs(i,&value);
+ *buffer++=value;
+ #ifdef EEPROM_DBG
+ printf("0x%04X: 0x%04X\n",i, value);
+ #else
+ if((i%0x10))
+ printf(".");
+ #endif
+ }
+ printf("\nDone\n");
+ return 0;
+}
+
+/******************************************************************************
+ * PCI Bridge Registers Dump
+*******************************************************************************/
+static void display_pci_regs(void)
+{
+ printf(" PCI9056_SPACE0_RANGE %08lX\n",PCICFG_GET_REG(PCI9056_SPACE0_RANGE));
+ printf(" PCI9056_SPACE0_REMAP %08lX\n",PCICFG_GET_REG(PCI9056_SPACE0_REMAP));
+ printf(" PCI9056_LOCAL_DMA_ARBIT %08lX\n",PCICFG_GET_REG(PCI9056_LOCAL_DMA_ARBIT));
+ printf(" PCI9056_ENDIAN_DESC %08lX\n",PCICFG_GET_REG(PCI9056_ENDIAN_DESC));
+ printf(" PCI9056_EXP_ROM_RANGE %08lX\n",PCICFG_GET_REG(PCI9056_EXP_ROM_RANGE));
+ printf(" PCI9056_EXP_ROM_REMAP %08lX\n",PCICFG_GET_REG(PCI9056_EXP_ROM_REMAP));
+ printf(" PCI9056_SPACE0_ROM_DESC %08lX\n",PCICFG_GET_REG(PCI9056_SPACE0_ROM_DESC));
+ printf(" PCI9056_DM_RANGE %08lX\n",PCICFG_GET_REG(PCI9056_DM_RANGE));
+ printf(" PCI9056_DM_MEM_BASE %08lX\n",PCICFG_GET_REG(PCI9056_DM_MEM_BASE));
+ printf(" PCI9056_DM_IO_BASE %08lX\n",PCICFG_GET_REG(PCI9056_DM_IO_BASE));
+ printf(" PCI9056_DM_PCI_MEM_REMAP %08lX\n",PCICFG_GET_REG(PCI9056_DM_PCI_MEM_REMAP));
+ printf(" PCI9056_DM_PCI_IO_CONFIG %08lX\n",PCICFG_GET_REG(PCI9056_DM_PCI_IO_CONFIG));
+ printf(" PCI9056_SPACE1_RANGE %08lX\n",PCICFG_GET_REG(PCI9056_SPACE1_RANGE));
+ printf(" PCI9056_SPACE1_REMAP %08lX\n",PCICFG_GET_REG(PCI9056_SPACE1_REMAP));
+ printf(" PCI9056_SPACE1_DESC %08lX\n",PCICFG_GET_REG(PCI9056_SPACE1_DESC));
+ printf(" PCI9056_DM_DAC %08lX\n",PCICFG_GET_REG(PCI9056_DM_DAC));
+ printf(" PCI9056_MAILBOX0 %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX0));
+ printf(" PCI9056_MAILBOX1 %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX1));
+ printf(" PCI9056_MAILBOX2 %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX2));
+ printf(" PCI9056_MAILBOX3 %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX3));
+ printf(" PCI9056_MAILBOX4 %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX4));
+ printf(" PCI9056_MAILBOX5 %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX5));
+ printf(" PCI9056_MAILBOX6 %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX6));
+ printf(" PCI9056_MAILBOX7 %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX7));
+ printf(" PCI9056_PCI_TO_LOC_DBELL %08lX\n",PCICFG_GET_REG(PCI9056_PCI_TO_LOC_DBELL));
+ printf(" PCI9056_LOC_TO_PCI_DBELL %08lX\n",PCICFG_GET_REG(PCI9056_LOC_TO_PCI_DBELL));
+ printf(" PCI9056_INT_CTRL_STAT %08lX\n",PCICFG_GET_REG(PCI9056_INT_CTRL_STAT));
+ printf(" PCI9056_EEPROM_CTRL_STAT %08lX\n",PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT));
+ printf(" PCI9056_PERM_VENDOR_ID %08lX\n",PCICFG_GET_REG(PCI9056_PERM_VENDOR_ID));
+ printf(" PCI9056_REVISION_ID %08lX\n",PCICFG_GET_REG(PCI9056_REVISION_ID));
+ printf(" \n");
+ printf(" PCI9056_VENDOR_ID %08lX\n",PCICFG_GET_REG(PCI9056_VENDOR_ID));
+ printf(" PCI9056_COMMAND %08lX\n",PCICFG_GET_REG(PCI9056_COMMAND));
+ printf(" PCI9056_REVISION %08lX\n",PCICFG_GET_REG(PCI9056_REVISION));
+ printf(" PCI9056_CACHE_SIZE %08lX\n",PCICFG_GET_REG(PCI9056_CACHE_SIZE));
+ printf(" PCI9056_RTR_BASE %08lX\n",PCICFG_GET_REG(PCI9056_RTR_BASE));
+ printf(" PCI9056_RTR_IO_BASE %08lX\n",PCICFG_GET_REG(PCI9056_RTR_IO_BASE));
+ printf(" PCI9056_LOCAL_BASE0 %08lX\n",PCICFG_GET_REG(PCI9056_LOCAL_BASE0));
+ printf(" PCI9056_LOCAL_BASE1 %08lX\n",PCICFG_GET_REG(PCI9056_LOCAL_BASE1));
+ printf(" PCI9056_UNUSED_BASE1 %08lX\n",PCICFG_GET_REG(PCI9056_UNUSED_BASE1));
+ printf(" PCI9056_UNUSED_BASE2 %08lX\n",PCICFG_GET_REG(PCI9056_UNUSED_BASE2));
+ printf(" PCI9056_CIS_PTR %08lX\n",PCICFG_GET_REG(PCI9056_CIS_PTR));
+ printf(" PCI9056_SUB_ID %08lX\n",PCICFG_GET_REG(PCI9056_SUB_ID));
+ printf(" PCI9056_EXP_ROM_BASE %08lX\n",PCICFG_GET_REG(PCI9056_EXP_ROM_BASE));
+ printf(" PCI9056_CAP_PTR %08lX\n",PCICFG_GET_REG(PCI9056_CAP_PTR));
+ printf(" PCI9056_INT_LINE %08lX\n",PCICFG_GET_REG(PCI9056_INT_LINE));
+ printf(" PCI9056_PM_CAP_ID %08lX\n",PCICFG_GET_REG(PCI9056_PM_CAP_ID));
+ printf(" PCI9056_PM_CSR %08lX\n",PCICFG_GET_REG(PCI9056_PM_CSR));
+ printf(" PCI9056_HS_CAP_ID %08lX\n",PCICFG_GET_REG(PCI9056_HS_CAP_ID));
+ printf(" PCI9056_VPD_CAP_ID %08lX\n",PCICFG_GET_REG(PCI9056_VPD_CAP_ID));
+ printf(" PCI9056_VPD_DATA %08lX\n",PCICFG_GET_REG(PCI9056_VPD_DATA));
+}
+
+
+int do_pati(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ if (strcmp(argv[1], "info") == 0)
+ {
+ show_pld_regs();
+ return 0;
+ }
+ if (strcmp(argv[1], "pci") == 0)
+ {
+ display_pci_regs();
+ return 0;
+ }
+ if (strcmp(argv[1], "led") == 0)
+ {
+ int led_nr,led_on;
+ led_nr = (int)simple_strtoul(argv[2], NULL, 10);
+ led_on = (int)simple_strtoul(argv[3], NULL, 10);
+ if(!led_nr)
+ user_led0(led_on);
+ else
+ user_led1(led_on);
+ return 0;
+ }
+#if defined(CONFIG_SYS_PCI_CON_DEVICE)
+ if (strcmp(argv[1], "con") == 0) {
+ pci_con_connect();
+ return 0;
+ }
+ if (strcmp(argv[1], "disc") == 0) {
+ pci_con_disc();
+ return 0;
+ }
+#endif
+ if (strcmp(argv[1], "eeprom") == 0) {
+ unsigned long addr;
+ int size, offset;
+ offset = 0;
+ size = PATI_EEPROM_LAST_OFFSET;
+ if(argc>2) {
+ if(argc>3) {
+ addr = simple_strtoul(argv[3], NULL, 16);
+ if(argc>4)
+ offset = (int) simple_strtoul(argv[4], NULL, 16);
+ if(argc>5)
+ size = (int) simple_strtoul(argv[5], NULL, 16);
+ if (strcmp(argv[2], "read") == 0) {
+ return (pati_pci_eeprom_read(offset, addr, size));
+ }
+ if (strcmp(argv[2], "write") == 0) {
+ return (pati_pci_eeprom_write(offset, addr, size));
+ }
+ }
+ if (strcmp(argv[2], "prg") == 0) {
+ return (pati_pci_eeprom_prg());
+ }
+ if (strcmp(argv[2], "era") == 0) {
+ return (pati_pci_eeprom_erase());
+ }
+ if (strcmp(argv[2], "reload") == 0) {
+ reload_pci_eeprom();
+ return 0;
+ }
+
+
+ }
+ }
+
+ return (do_mplcommon(cmdtp, flag, argc, argv));
+}
+
+U_BOOT_CMD(
+ pati, 8, 1, do_pati,
+ "PATI specific Cmds",
+ "info - displays board information\n"
+ "pati pci - displays PCI registers\n"
+ "pati led <nr> <on> \n"
+ " - switch LED <nr> <on>\n"
+ "pati flash mem [SrcAddr]\n"
+ " - updates U-Boot with image in memory\n"
+ "pati eeprom <cmd> - PCI EEPROM sub-system\n"
+ " read <addr> <offset> <size>\n"
+ " - read PCI EEPROM to <addr> from <offset> <size> words\n"
+ " write <addr> <offset> <size>\n"
+ " - write PCI EEPROM from <addr> to <offset> <size> words\n"
+ " prg - programm PCI EEPROM with default values\n"
+ " era - erase PCI EEPROM (write all word to 0xffff)\n"
+ " reload- Reload PCI Bridge with EEPROM Values\n"
+ " NOTE: <addr> must start on word boundary\n"
+ " <offset> and <size> must be even byte values"
+);
+
+/* ------------------------------------------------------------------------- */
diff --git a/board/mpl/pati/pati.c b/board/mpl/pati/pati.c
new file mode 100644
index 0000000000..1288f743cc
--- /dev/null
+++ b/board/mpl/pati/pati.c
@@ -0,0 +1,610 @@
+/*
+ * (C) Copyright 2003
+ * Martin Winistoerfer, martinwinistoerfer at gmx.ch.
+ * Atapted for PATI
+ * Denis Peter, d.peter at mpl.ch
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/***********************************************************************************
+ * Bits for the SDRAM controller
+ * -----------------------------
+ *
+ * CAL: CAS Latency. If cleared to 0 (default) the SDRAM controller asserts TA# on
+ * the 2nd Clock after ACTIVE command (CAS Latency = 2). If set to 1 the SDRAM
+ * controller asserts TA# on the 3rd Clock after ACTIVE command (CAS Latency = 3).
+ * RCD: RCD ACTIVE to READ or WRITE Delay (Ras to Cas Delay). If cleared 0 (default)
+ * tRCD of the SDRAM must equal or less 25ns. If set to 1 tRCD must be equal or less 50ns.
+ * WREC:Write Recovery. If cleared 0 (default) tWR of the SDRAM must equal or less 25ns.
+ * If set to 1 tWR must be equal or less 50ns.
+ * RP: Precharge Command Time. If cleared 0 (default) tRP of the SDRAM must equal or less
+ * 25ns. If set to 1 tRP must be equal or less 50ns.
+ * RC: Auto Refresh to Active Time. If cleared 0 (default) tRC of the SDRAM must equal
+ * or less 75ns. If set to 1 tRC must be equal or less 100ns.
+ * LMR: Bit to set the Mode Register of the SDRAM. If set, the next access to the SDRAM
+ * is the Load Mode Register Command.
+ * IIP: Init in progress. Set to 1 for starting the init sequence
+ * (Precharge All). As long this bit is set, the Precharge All is still in progress.
+ * After command has completed, wait at least for 8 refresh (200usec) before proceed.
+ **********************************************************************************/
+
+#include <common.h>
+#include <console.h>
+#include <mpc5xx.h>
+#include <stdio_dev.h>
+#include <pci_ids.h>
+#define PLX9056_LOC
+#include "plx9056.h"
+#include "pati.h"
+
+#if defined(__APPLE__)
+/* Leading underscore on symbols */
+# define SYM_CHAR "_"
+#else /* No leading character on symbols */
+# define SYM_CHAR
+#endif
+
+#undef SDRAM_DEBUG
+/*
+ * Macros to generate global absolutes.
+ */
+#define GEN_SYMNAME(str) SYM_CHAR #str
+#define GEN_VALUE(str) #str
+#define GEN_ABS(name, value) \
+ asm (".globl " GEN_SYMNAME(name)); \
+ asm (GEN_SYMNAME(name) " = " GEN_VALUE(value))
+
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/************************************************************************
+ * Early debug routines
+ */
+void write_hex (unsigned char i)
+{
+ char cc;
+
+ cc = i >> 4;
+ cc &= 0xf;
+ if (cc > 9)
+ serial_putc (cc + 55);
+ else
+ serial_putc (cc + 48);
+ cc = i & 0xf;
+ if (cc > 9)
+ serial_putc (cc + 55);
+ else
+ serial_putc (cc + 48);
+}
+
+#if defined(SDRAM_DEBUG)
+
+void write_4hex (unsigned long val)
+{
+ write_hex ((unsigned char) (val >> 24));
+ write_hex ((unsigned char) (val >> 16));
+ write_hex ((unsigned char) (val >> 8));
+ write_hex ((unsigned char) val);
+}
+
+#endif
+
+unsigned long in32(unsigned long addr)
+{
+ unsigned long *p=(unsigned long *)addr;
+ return *p;
+}
+
+void out32(unsigned long addr,unsigned long data)
+{
+ unsigned long *p=(unsigned long *)addr;
+ *p=data;
+}
+
+typedef struct {
+ unsigned short boardtype; /* Board revision and Population Options */
+ unsigned char cal; /* cas Latency 0:CAL=2 1:CAL=3 */
+ unsigned char rcd; /* ras to cas delay 0:<25ns 1:<50ns*/
+ unsigned char wrec; /* write recovery 0:<25ns 1:<50ns */
+ unsigned char pr; /* Precharge Command Time 0:<25ns 1:<50ns */
+ unsigned char rc; /* Auto Refresh to Active Time 0:<75ns 1:<100ns */
+ unsigned char sz; /* log binary => Size = (4MByte<<sz) 5 = 128, 4 = 64, 3 = 32, 2 = 16, 1=8 */
+} sdram_t;
+
+const sdram_t sdram_table[] = {
+ { 0x0000, /* PATI Rev A, 16MByte -1 Board */
+ 1, /* Case Latenty = 3 */
+ 0, /* ras to cas delay 0 (20ns) */
+ 0, /* write recovery 0:<25ns 1:<50ns*/
+ 0, /* Precharge Command Time 0 (20ns) */
+ 0, /* Auto Refresh to Active Time 0 (68) */
+ 2 /* log binary => Size 2 = 16MByte, 1=8 */
+ },
+ { 0xffff, /* terminator */
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff }
+};
+
+
+extern int mem_test (unsigned long start, unsigned long ramsize, int quiet);
+
+/*
+ * Get RAM size.
+ */
+int dram_init(void)
+{
+ unsigned char board_rev;
+ unsigned long reg;
+ unsigned long lmr;
+ int i,timeout;
+
+#if defined(SDRAM_DEBUG)
+ reg=in32(PLD_CONFIG_BASE+PLD_PART_ID);
+ puts("\n\nSYSTEM part 0x"); write_4hex(SYSCNTR_PART(reg));
+ puts(" Vers 0x"); write_4hex(SYSCNTR_ID(reg));
+ puts("\nSDRAM part 0x"); write_4hex(SDRAM_PART(reg));
+ puts(" Vers 0x"); write_4hex(SDRAM_ID(reg));
+ reg=in32(PLD_CONFIG_BASE+PLD_BOARD_TIMING);
+ puts("\nBoard rev. 0x"); write_4hex(SYSCNTR_BREV(reg));
+ putc('\n');
+#endif
+ reg=in32(PLD_CONFIG_BASE+PLD_BOARD_TIMING);
+ board_rev=(unsigned char)(SYSCNTR_BREV(reg));
+ i=0;
+ while(1) {
+ if(sdram_table[i].boardtype==0xffff) {
+ puts("ERROR, found no table for Board 0x");
+ write_hex(board_rev);
+ while(1);
+ }
+ if(sdram_table[i].boardtype==(unsigned char)board_rev)
+ break;
+ i++;
+ }
+ /* Set CAL, RCD, WREQ, PR and RC Bits */
+#if defined(SDRAM_DEBUG)
+ puts("Set CAL, RCD, WREQ, PR and RC Bits\n");
+#endif
+ /* mask bits */
+ reg &= ~(SET_REG_BIT(1,SDRAM_CAL) | SET_REG_BIT(1,SDRAM_RCD) | SET_REG_BIT(1,SDRAM_WREQ) |
+ SET_REG_BIT(1,SDRAM_PR) | SET_REG_BIT(1,SDRAM_RC) | SET_REG_BIT(1,SDRAM_LMR) |
+ SET_REG_BIT(1,SDRAM_IIP) | SET_REG_BIT(1,SDRAM_RES0));
+ /* set bits */
+ reg |= (SET_REG_BIT(sdram_table[i].cal,SDRAM_CAL) |
+ SET_REG_BIT(sdram_table[i].rcd,SDRAM_RCD) |
+ SET_REG_BIT(sdram_table[i].wrec,SDRAM_WREQ) |
+ SET_REG_BIT(sdram_table[i].pr,SDRAM_PR) |
+ SET_REG_BIT(sdram_table[i].rc,SDRAM_RC));
+
+ out32(PLD_CONFIG_BASE+PLD_BOARD_TIMING,reg);
+ /* step 2 set IIP */
+#if defined(SDRAM_DEBUG)
+ puts("step 2 set IIP\n");
+#endif
+ /* step 2 set IIP */
+ reg |= SET_REG_BIT(1,SDRAM_IIP);
+ timeout=0;
+ while (timeout!=0xffff) {
+ __asm__ volatile("eieio");
+ reg=in32(PLD_CONFIG_BASE+PLD_BOARD_TIMING);
+ if((reg & SET_REG_BIT(1,SDRAM_IIP))==0)
+ break;
+ timeout++;
+ udelay(1);
+ }
+ /* wait for at least 8 refresh */
+ udelay(1000);
+ /* set LMR */
+ reg |= SET_REG_BIT(1,SDRAM_LMR);
+ out32(PLD_CONFIG_BASE+PLD_BOARD_TIMING,reg);
+ __asm__ volatile("eieio");
+ lmr=0x00000002; /* sequential burst 4 data */
+ if(sdram_table[i].cal==1)
+ lmr|=0x00000030; /* cal = 3 */
+ else
+ lmr|=0000000020; /* cal = 2 */
+ /* rest standard operation programmed write burst length */
+ /* we have a x32 bit bus to the SDRAM, so shift the addr with 2 */
+ lmr<<=2;
+ in32(CONFIG_SYS_SDRAM_BASE + lmr);
+ /* ok, we're done, set SDRAM size to log2 value of 4MByte*/
+ gd->ram_size = 0x400000 << sdram_table[i].sz;
+
+ return 0;
+}
+
+
+void set_flash_vpp(int ext_vpp, int ext_wp, int int_vpp)
+{
+ unsigned long reg;
+ reg=in32(PLD_CONF_REG2+PLD_CONFIG_BASE);
+ reg &= ~(SET_REG_BIT(1,SYSCNTR_CPU_VPP) |
+ SET_REG_BIT(1,SYSCNTR_FL_VPP) |
+ SET_REG_BIT(1,SYSCNTR_FL_WP));
+
+ reg |= (SET_REG_BIT(int_vpp,SYSCNTR_CPU_VPP) |
+ SET_REG_BIT(ext_vpp,SYSCNTR_FL_VPP) |
+ SET_REG_BIT(ext_wp,SYSCNTR_FL_WP));
+ out32(PLD_CONF_REG2+PLD_CONFIG_BASE,reg);
+ udelay(100);
+}
+
+
+void show_pld_regs(void)
+{
+ unsigned long reg,reg1;
+ reg=in32(PLD_CONFIG_BASE+PLD_PART_ID);
+ printf("\nSYSTEM part %ld, Vers %ld\n",SYSCNTR_PART(reg),SYSCNTR_ID(reg));
+ printf("SDRAM part %ld, Vers %ld\n",SDRAM_PART(reg),SDRAM_ID(reg));
+ reg=in32(PLD_CONFIG_BASE+PLD_BOARD_TIMING);
+ printf("Board rev. %c\n",(char) (SYSCNTR_BREV(reg)+'A'));
+ printf("Waitstates %ld\n",GET_SYSCNTR_FLWAIT(reg));
+ printf("SDRAM: CAL=%ld RCD=%ld WREQ=%ld PR=%ld\n RC=%ld LMR=%ld IIP=%ld\n",
+ GET_REG_BIT(reg,SDRAM_CAL),GET_REG_BIT(reg,SDRAM_RCD),
+ GET_REG_BIT(reg,SDRAM_WREQ),GET_REG_BIT(reg,SDRAM_PR),
+ GET_REG_BIT(reg,SDRAM_RC),GET_REG_BIT(reg,SDRAM_LMR),
+ GET_REG_BIT(reg,SDRAM_IIP));
+ reg=in32(PLD_CONFIG_BASE+PLD_CONF_REG1);
+ reg1=in32(PLD_CONFIG_BASE+PLD_CONF_REG2);
+ printf("HW Config: FLAG=%ld IP=%ld index=%ld PRPM=%ld\n ICW=%ld ISB=%ld BDIS=%ld PCIM=%ld\n",
+ GET_REG_BIT(reg,SYSCNTR_FLAG),GET_REG_BIT(reg,SYSCNTR_IP),
+ GET_SYSCNTR_BOOTIND(reg),GET_REG_BIT(reg,SYSCNTR_PRM),
+ GET_REG_BIT(reg,SYSCNTR_ICW),GET_SYSCNTR_ISB(reg),
+ GET_REG_BIT(reg1,SYSCNTR_BDIS),GET_REG_BIT(reg1,SYSCNTR_PCIM));
+ printf("Switches: MUX=%ld PCI_DIS=%ld Boot_EN=%ld Config=%ld\n",GET_SDRAM_MUX(reg),
+ GET_REG_BIT(reg,SDRAM_PDIS),GET_REG_BIT(reg1,SYSCNTR_BOOTEN),
+ GET_SYSCNTR_CFG(reg1));
+ printf("Misc: RIP=%ld CPU_VPP=%ld FLSH_VPP=%ld FLSH_WP=%ld\n\n",
+ GET_REG_BIT(reg,SDRAM_RIP),GET_REG_BIT(reg1,SYSCNTR_CPU_VPP),
+ GET_REG_BIT(reg1,SYSCNTR_FL_VPP),GET_REG_BIT(reg1,SYSCNTR_FL_WP));
+}
+
+
+/****************************************************************
+ * Setting IOs
+ * -----------
+ * GPIO6 is User LED1
+ * GPIO7 is Interrupt PLX (Output)
+ * GPIO5 is User LED0
+ * GPIO2 is PLX USERi (Output)
+ * GPIO1 is PLX Interrupt (Input)
+ ****************************************************************/
+ void init_ios(void)
+ {
+ volatile immap_t * immr = (immap_t *) CONFIG_SYS_IMMR;
+ volatile sysconf5xx_t *sysconf = &immr->im_siu_conf;
+ unsigned long reg;
+ reg=sysconf->sc_sgpiocr; /* Data direction register */
+ reg &= ~0x67000000;
+ reg |= 0x27000000; /* set outpupts */
+ sysconf->sc_sgpiocr=reg; /* Data direction register */
+ reg=sysconf->sc_sgpiodt2; /* Data register */
+ /* set output to 0 */
+ reg &= ~0x27000000;
+ /* set IRQ and USERi to 1 */
+ reg |= 0x28000000;
+ sysconf->sc_sgpiodt2=reg; /* Data register */
+}
+
+void user_led0(int led_on)
+{
+ volatile immap_t * immr = (immap_t *) CONFIG_SYS_IMMR;
+ volatile sysconf5xx_t *sysconf = &immr->im_siu_conf;
+ unsigned long reg;
+ reg=sysconf->sc_sgpiodt2; /* Data register */
+ if(led_on) /* set output to 1 */
+ reg |= 0x04000000;
+ else
+ reg &= ~0x04000000;
+ sysconf->sc_sgpiodt2=reg; /* Data register */
+}
+
+void user_led1(int led_on)
+{
+ volatile immap_t * immr = (immap_t *) CONFIG_SYS_IMMR;
+ volatile sysconf5xx_t *sysconf = &immr->im_siu_conf;
+ unsigned long reg;
+ reg=sysconf->sc_sgpiodt2; /* Data register */
+ if(led_on) /* set output to 1 */
+ reg |= 0x02000000;
+ else
+ reg &= ~0x02000000;
+ sysconf->sc_sgpiodt2=reg; /* Data register */
+}
+
+int board_early_init_f(void)
+{
+ spi_init_f();
+ return 0;
+}
+
+/****************************************************************
+ * Last Stage Init
+ ****************************************************************/
+int last_stage_init (void)
+{
+ init_ios();
+ return 0;
+}
+
+/****************************************************************
+ * Check the board
+ ****************************************************************/
+
+#define BOARD_NAME "PATI"
+
+int checkboard (void)
+{
+ char s[50];
+ ulong reg;
+ char rev;
+ int i;
+
+ puts ("\nBoard: ");
+ reg=in32(PLD_CONFIG_BASE+PLD_BOARD_TIMING);
+ rev=(char)(SYSCNTR_BREV(reg)+'A');
+ i = getenv_f("serial#", s, 32);
+ if ((i == -1)) {
+ puts ("### No HW ID - assuming " BOARD_NAME);
+ printf(" Rev. %c\n",rev);
+ }
+ else {
+ s[sizeof(BOARD_NAME)-1] = 0;
+ printf ("%s-1 Rev %c SN: %s\n", s,rev,
+ &s[sizeof(BOARD_NAME)]);
+ }
+ set_flash_vpp(1,0,0); /* set Flash VPP */
+ return 0;
+}
+
+
+#ifdef CONFIG_SYS_PCI_CON_DEVICE
+/************************************************************************
+ * PCI Communication
+ *
+ * Alive (Pinging):
+ * ----------------
+ * PCI Host sends message ALIVE, Local acknowledges with ALIVE
+ *
+ * PCI_CON console over PCI:
+ * -------------------------
+ * Local side:
+ * - uses PCI9056_LOC_TO_PCI_DBELL register to signal that
+ * data is avaible (PCIMSG_CONN)
+ * - uses PCI9056_MAILBOX1 to send data
+ * - uses PCI9056_MAILBOX0 to receive data
+ * PCI side:
+ * - uses PCI9056_PCI_TO_LOC_DBELL register to signal that
+ * data is avaible (PCIMSG_CONN)
+ * - uses PCI9056_MAILBOX0 to send data
+ * - uses PCI9056_MAILBOX1 to receive data
+ *
+ * How it works:
+ * Send:
+ * - check if PCICON_TRANSMIT_REG is empty
+ * - write data or'ed with 0x80000000 into the PCICON_TRANSMIT_REG
+ * - write PCIMSG_CONN into the PCICON_DBELL_REG to signal a data
+ * is waiting
+ * Receive:
+ * - get an interrupt via the PCICON_ACK_REG register message
+ * PCIMSG_CONN
+ * - write the data from the PCICON_RECEIVE_REG into the receive
+ * buffer and if the receive buffer is not full, clear the
+ * PCICON_RECEIVE_REG (this allows the counterpart to write more data)
+ * - Clear the interrupt by writing 0xFFFFFFFF to the PCICON_ACK_REG
+ *
+ * The PCICON_RECEIVE_REG must be cleared by the routine which reads
+ * the receive buffer if the buffer is not full any more
+ *
+ */
+
+#undef PCI_CON_DEBUG
+
+#ifdef PCI_CON_DEBUG
+#define PCI_CON_PRINTF(fmt,args...) serial_printf (fmt ,##args)
+#else
+#define PCI_CON_PRINTF(fmt,args...)
+#endif
+
+
+/*********************************************************
+ * we work only with a receive buffer on eiter side.
+ * Transmit buffer is free, if mailbox is cleared.
+ * Transmit character is or'ed with 0x80000000
+ * PATI receive register MAILBOX0
+ * PATI transmit register MAILBOX1
+ *********************************************************/
+#define PCICON_RECEIVE_REG PCI9056_MAILBOX0
+#define PCICON_TRANSMIT_REG PCI9056_MAILBOX1
+#define PCICON_DBELL_REG PCI9056_LOC_TO_PCI_DBELL
+#define PCICON_ACK_REG PCI9056_PCI_TO_LOC_DBELL
+
+
+#define PCIMSG_ALIVE 0x1
+#define PCIMSG_CONN 0x2
+#define PCIMSG_DISC 0x3
+#define PCIMSG_CON_DATA 0x5
+
+
+#define PCICON_GET_REG(x) (in32(x + PCI_CONFIG_BASE))
+#define PCICON_SET_REG(x,y) (out32(x + PCI_CONFIG_BASE,y))
+#define PCICON_TX_FLAG 0x80000000
+
+
+#define REC_BUFFER_SIZE 0x100
+int recbuf[REC_BUFFER_SIZE];
+static int r_ptr = 0;
+int w_ptr;
+struct stdio_dev pci_con_dev;
+int conn=0;
+int buff_full=0;
+
+void pci_con_put_it(const char c)
+{
+ /* Test for completition */
+ unsigned long reg;
+ do {
+ reg=PCICON_GET_REG(PCICON_TRANSMIT_REG);
+ }while(reg);
+ reg=PCICON_TX_FLAG + c;
+ PCICON_SET_REG(PCICON_TRANSMIT_REG,reg);
+ PCICON_SET_REG(PCICON_DBELL_REG,PCIMSG_CON_DATA);
+}
+
+void pci_con_putc(struct stdio_dev *dev, const char c)
+{
+ pci_con_put_it(c);
+ if(c == '\n')
+ pci_con_put_it('\r');
+}
+
+
+int pci_con_getc(struct stdio_dev *dev)
+{
+ int res;
+ int diff;
+ while(r_ptr==(volatile int)w_ptr);
+ res=recbuf[r_ptr++];
+ if(r_ptr==REC_BUFFER_SIZE)
+ r_ptr=0;
+ if(w_ptr<r_ptr)
+ diff=r_ptr+REC_BUFFER_SIZE-w_ptr;
+ else
+ diff=r_ptr-w_ptr;
+ if((diff<(REC_BUFFER_SIZE-4)) && buff_full) {
+ /* clear Mail box */
+ buff_full=0;
+ PCICON_SET_REG(PCICON_RECEIVE_REG,0L);
+ }
+ return res;
+}
+
+int pci_con_tstc(struct stdio_dev *dev)
+{
+ if(r_ptr==(volatile int)w_ptr)
+ return 0;
+ return 1;
+}
+
+void pci_con_puts(struct stdio_dev *dev, const char *s)
+{
+ while (*s) {
+ pci_con_putc(*s);
+ ++s;
+ }
+}
+
+void pci_con_init (void)
+{
+ w_ptr = 0;
+ r_ptr = 0;
+ PCICON_SET_REG(PCICON_RECEIVE_REG,0L);
+ conn=1;
+}
+
+/*******************************************
+ * IRQ routine
+ ******************************************/
+int pci_dorbell_irq(void)
+{
+ unsigned long reg,data;
+ int diff;
+ reg=PCICON_GET_REG(PCI9056_INT_CTRL_STAT);
+ PCI_CON_PRINTF(" PCI9056_INT_CTRL_STAT = %08lX\n",reg);
+ if(reg & (1<<20) ) {
+ /* read doorbell */
+ reg=PCICON_GET_REG(PCICON_ACK_REG);
+ switch(reg) {
+ case PCIMSG_ALIVE:
+ PCI_CON_PRINTF(" Alive\n");
+ PCICON_SET_REG(PCICON_DBELL_REG,PCIMSG_ALIVE);
+ break;
+ case PCIMSG_CONN:
+ PCI_CON_PRINTF(" Conn %d",conn);
+ w_ptr = 0;
+ r_ptr = 0;
+ buff_full=0;
+ PCICON_SET_REG(PCICON_RECEIVE_REG,0L);
+ conn=1;
+ PCI_CON_PRINTF(" ... %d\n",conn);
+ break;
+ case PCIMSG_CON_DATA:
+ data=PCICON_GET_REG(PCICON_RECEIVE_REG);
+ recbuf[w_ptr++]=(int)(data&0xff);
+ PCI_CON_PRINTF(" Data Console %lX, %X %d %d %X\n",data,((int)(data&0xFF)),
+ r_ptr,w_ptr,recbuf[w_ptr-1]);
+ if(w_ptr==REC_BUFFER_SIZE)
+ w_ptr=0;
+ if(w_ptr<r_ptr)
+ diff=r_ptr+REC_BUFFER_SIZE-w_ptr;
+ else
+ diff=r_ptr-w_ptr;
+ if(diff>(REC_BUFFER_SIZE-4))
+ buff_full=1;
+ else
+ /* clear Mail box */
+ PCICON_SET_REG(PCICON_RECEIVE_REG,0L);
+ break;
+ default:
+ serial_printf(" PCI9056_PCI_TO_LOC_DBELL = %08lX\n",reg);
+ }
+ /* clear IRQ */
+ PCICON_SET_REG(PCICON_ACK_REG,~0L);
+ }
+ return 0;
+}
+
+void pci_con_connect(void)
+{
+ unsigned long reg;
+ conn=0;
+ reg=PCICON_GET_REG(PCI9056_INT_CTRL_STAT);
+ /* default 0x0f010180 */
+ reg &= 0xff000000;
+ reg |= 0x00030000; /* enable local dorbell */
+ reg |= 0x00000300; /* enable PCI dorbell */
+ PCICON_SET_REG(PCI9056_INT_CTRL_STAT , reg);
+ irq_install_handler (0x2, (interrupt_handler_t *) pci_dorbell_irq,NULL);
+ memset (&pci_con_dev, 0, sizeof (pci_con_dev));
+ strcpy (pci_con_dev.name, "pci_con");
+ pci_con_dev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_INPUT;
+ pci_con_dev.putc = pci_con_putc;
+ pci_con_dev.puts = pci_con_puts;
+ pci_con_dev.getc = pci_con_getc;
+ pci_con_dev.tstc = pci_con_tstc;
+ stdio_register (&pci_con_dev);
+ printf("PATI ready for PCI connection, type ctrl-c for exit\n");
+ do {
+ udelay(10);
+ if((volatile int)conn)
+ break;
+ if(ctrlc()) {
+ irq_free_handler(0x2);
+ return;
+ }
+ }while(1);
+ console_assign(stdin,"pci_con");
+ console_assign(stderr,"pci_con");
+ console_assign(stdout,"pci_con");
+}
+
+void pci_con_disc(void)
+{
+ console_assign(stdin,"serial");
+ console_assign(stderr,"serial");
+ console_assign(stdout,"serial");
+ PCICON_SET_REG(PCICON_DBELL_REG,PCIMSG_DISC);
+ /* reconnection */
+ irq_free_handler(0x02);
+ pci_con_connect();
+}
+#endif /* #ifdef CONFIG_SYS_PCI_CON_DEVICE */
+
+/*
+ * Absolute environment address for linker file.
+ */
+GEN_ABS(env_start, CONFIG_ENV_OFFSET + CONFIG_SYS_FLASH_BASE);
diff --git a/board/mpl/pati/pati.h b/board/mpl/pati/pati.h
new file mode 100644
index 0000000000..93a5918252
--- /dev/null
+++ b/board/mpl/pati/pati.h
@@ -0,0 +1,423 @@
+/*
+ * (C) Copyright 2003
+ * Denis Peter, d.peter at mpl.ch
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+/************************************************************************
+ * MACROS and register definitions for PATI Registers
+ ************************************************************************/
+#ifndef __PATI_H_
+#define __PATI_H_ 1
+
+#define PLD_PART_ID 0x0
+#define PLD_BOARD_TIMING 0x4
+#define PLD_CONF_REG1 0x8
+#define PLD_CONF_REG2 0xC
+#define PLD_CONF_RES 0x10
+
+#define SET_REG_BIT(y,x) (y<<(31-x))
+#define GET_REG_BIT(y,x) ((y>>(31-x)) & 0x1L)
+
+/* SDRAM Controller PLD_PART_ID */
+/* 9 10 11 12 13 14 19 31 */
+#define SDRAM_PART3 9
+#define SDRAM_PART2 10
+#define SDRAM_PART1 11
+#define SDRAM_PART0 12
+#define SDRAM_ID3 13
+#define SDRAM_ID2 14
+#define SDRAM_ID1 19
+#define SDRAM_ID0 31
+
+#define SDRAM_PART(x) ( \
+ (GET_REG_BIT(x,SDRAM_PART3)<<3) |\
+ (GET_REG_BIT(x,SDRAM_PART2)<<2) |\
+ (GET_REG_BIT(x,SDRAM_PART1)<<1) |\
+ (GET_REG_BIT(x,SDRAM_PART0)))
+
+#define SDRAM_ID(x) ( \
+ (GET_REG_BIT(x,SDRAM_ID3)<<3) |\
+ (GET_REG_BIT(x,SDRAM_ID2)<<2) |\
+ (GET_REG_BIT(x,SDRAM_ID1)<<1) |\
+ (GET_REG_BIT(x,SDRAM_ID0)))
+
+/* System Controller */
+/* 0 1 3 4 5 16 20 28 29 30 */
+#define SYSCNTR_PART4 0
+#define SYSCNTR_PART3 1
+#define SYSCNTR_PART2 3
+#define SYSCNTR_PART1 4
+#define SYSCNTR_PART0 5
+#define SYSCNTR_ID4 16
+#define SYSCNTR_ID3 20
+#define SYSCNTR_ID2 28
+#define SYSCNTR_ID1 29
+#define SYSCNTR_ID0 30
+
+#define SYSCNTR_PART(x) ( \
+ (GET_REG_BIT(x,SYSCNTR_PART4)<<4) |\
+ (GET_REG_BIT(x,SYSCNTR_PART3)<<3) |\
+ (GET_REG_BIT(x,SYSCNTR_PART2)<<2) |\
+ (GET_REG_BIT(x,SYSCNTR_PART1)<<1) |\
+ (GET_REG_BIT(x,SYSCNTR_PART0)))
+
+#define SYSCNTR_ID(x) ( \
+ (GET_REG_BIT(x,SYSCNTR_ID4)<<4) |\
+ (GET_REG_BIT(x,SYSCNTR_ID3)<<3) |\
+ (GET_REG_BIT(x,SYSCNTR_ID2)<<2) |\
+ (GET_REG_BIT(x,SYSCNTR_ID1)<<1) |\
+ (GET_REG_BIT(x,SYSCNTR_ID0)))
+
+/* SDRAM Controller PLD_BOARD_TIMING */
+/* 9 10 11 12 13 14 19 31 */
+#define SDRAM_CAL 9
+#define SDRAM_RCD 10
+#define SDRAM_WREQ 11
+#define SDRAM_PR 12
+#define SDRAM_RC 13
+#define SDRAM_LMR 14
+#define SDRAM_IIP 19
+#define SDRAM_RES0 31
+/* System Controller */
+/* 0 1 3 4 5 16 20 28 29 30 */
+#define SYSCNTR_BREV0 0
+#define SYSCNTR_BREV1 1
+#define SYSCNTR_BREV2 3
+#define SYSCNTR_BREV3 4
+#define SYSCNTR_RES0 5
+#define SYSCNTR_RES1 16
+#define SYSCNTR_RES2 20
+#define SYSCNTR_FLWAIT2 28
+#define SYSCNTR_FLWAIT1 29
+#define SYSCNTR_FLWAIT0 30
+
+#define SYSCNTR_BREV(x) ( \
+ (GET_REG_BIT(x,SYSCNTR_BREV3)<<3) |\
+ (GET_REG_BIT(x,SYSCNTR_BREV2)<<2) |\
+ (GET_REG_BIT(x,SYSCNTR_BREV1)<<1) |\
+ (GET_REG_BIT(x,SYSCNTR_BREV0)))
+
+#define GET_SYSCNTR_FLWAIT(x) ( \
+ (GET_REG_BIT(x,SYSCNTR_FLWAIT2)<<2) |\
+ (GET_REG_BIT(x,SYSCNTR_FLWAIT1)<<1) |\
+ (GET_REG_BIT(x,SYSCNTR_FLWAIT0)))
+
+#define SET_SYSCNTR_FLWAIT(x) ( \
+ (SET_REG_BIT(((x & 0x04)!=0),SYSCNTR_FLWAIT2)) |\
+ (SET_REG_BIT(((x & 0x02)!=0)x,SYSCNTR_FLWAIT1)) |\
+ (SET_REG_BIT(((x & 0x01)!=0)x,SYSCNTR_FLWAIT0)))
+
+/* SDRAM Controller REG 2*/
+/* 9 10 11 12 13 14 19 31 */
+#define SDRAM_MUX0 9
+#define SDRAM_MUX1 10
+#define SDRAM_PDIS 11
+#define SDRAM_RES1 12
+#define SDRAM_RES2 13
+#define SDRAM_RES3 14
+#define SDRAM_RES4 19
+#define SDRAM_RIP 31
+
+#define GET_SDRAM_MUX(x) ( \
+ (GET_REG_BIT(x,SDRAM_MUX1)<<1)| \
+ (GET_REG_BIT(x,SDRAM_MUX0)))
+
+
+/* System Controller */
+/* 0 1 3 4 5 16 20 28 29 30 */
+#define SYSCNTR_FLAG 0
+#define SYSCNTR_IP 1
+#define SYSCNTR_BIND2 3
+#define SYSCNTR_BIND1 4
+#define SYSCNTR_BIND0 5
+#define SYSCNTR_PRM 16
+#define SYSCNTR_ICW 20
+#define SYSCNTR_ISB2 28
+#define SYSCNTR_ISB1 29
+#define SYSCNTR_ISB0 30
+
+#define GET_SYSCNTR_BOOTIND(x) ( \
+ (GET_REG_BIT(x,SYSCNTR_BIND2)<<2) |\
+ (GET_REG_BIT(x,SYSCNTR_BIND1)<<1) |\
+ (GET_REG_BIT(x,SYSCNTR_BIND0)))
+
+#define SET_SYSCNTR_BOOTIND(x) ( \
+ (SET_REG_BIT(((x & 0x04)!=0),SYSCNTR_BIND2)) |\
+ (SET_REG_BIT(((x & 0x02)!=0)x,SYSCNTR_BIND1))| \
+ (SET_REG_BIT(((x & 0x01)!=0)x,SYSCNTR_BIND0)))
+
+#define GET_SYSCNTR_ISB(x) ( \
+ (GET_REG_BIT(x,SYSCNTR_ISB2)<<2)| \
+ (GET_REG_BIT(x,SYSCNTR_ISB1)<<1)| \
+ (GET_REG_BIT(x,SYSCNTR_ISB0)))
+
+#define SET_SYSCNTR_ISB(x) ( \
+ (SET_REG_BIT(((x & 0x04)!=0),SYSCNTR_ISB2))| \
+ (SET_REG_BIT(((x & 0x02)!=0)x,SYSCNTR_ISB))| \
+ (SET_REG_BIT(((x & 0x01)!=0)x,SYSCNTR_ISB0)))
+
+/* SDRAM Controller REG 3*/
+/* 9 10 11 12 13 14 19 31 */
+#define SDRAM_RES5 9
+#define SDRAM_CFG1 10
+#define SDRAM_CFG2 11
+#define SDRAM_CFG3 12
+#define SDRAM_RES6 13
+#define SDRAM_CFG5 14
+#define SDRAM_CFG6 19
+#define SDRAM_RES7 31
+
+#define GET_SDRAM_CFG(x) ( \
+ (GET_REG_BIT(x,SDRAM_CFG6)<<4) |\
+ (GET_REG_BIT(x,SDRAM_CFG5)<<3) |\
+ (GET_REG_BIT(x,SDRAM_CFG3)<<2) |\
+ (GET_REG_BIT(x,SDRAM_CFG2)<<1) |\
+ (GET_REG_BIT(x,SDRAM_CFG1)))
+
+/* System Controller */
+/* 0 1 3 4 5 16 20 28 29 30 */
+#define SYSCNTR_BDIS 0
+#define SYSCNTR_PCIM 1
+#define SYSCNTR_CFG0 3
+#define SYSCNTR_CFG1 4
+#define SYSCNTR_CFG2 5
+#define SYSCNTR_CFG3 16
+#define SYSCNTR_BOOTEN 20
+#define SYSCNTR_CPU_VPP 28
+#define SYSCNTR_FL_VPP 29
+#define SYSCNTR_FL_WP 30
+
+#define GET_SYSCNTR_CFG(x) ( \
+ (GET_REG_BIT(x,SYSCNTR_CFG3)<<3)| \
+ (GET_REG_BIT(x,SYSCNTR_CFG2)<<2)| \
+ (GET_REG_BIT(x,SYSCNTR_CFG1)<<1)| \
+ (GET_REG_BIT(x,SYSCNTR_CFG0)))
+
+
+/***************************************************************
+ * MISC Defines
+ ***************************************************************/
+
+#define PCI_VENDOR_ID_MPL 0x18E6
+#define PCI_DEVICE_ID_PATI 0x00DA
+
+#if defined(CONFIG_TARGET_MIP405) || defined(CONFIG_TARGET_MIP405T)
+#define PATI_FIRMWARE_START_OFFSET 0x00300000
+#endif
+
+#define PATI_ENDIAN_MODE 0x3E
+
+/*******************************************
+ * PATI Mapping:
+ * -------------
+ * PCI Map:
+ * -------
+ * All addreses are mapped into the memory area
+ * (IO Area on some areas may also be possible)
+ * - pci_cfg_mem_base: fixed address to the PLX config area size 512Bytes
+ * - pci_space0_addr: configurable
+ * - pci_space1_addr configurable
+ *
+ * Local Map:
+ * ----------
+ * Local addresses (Remap)
+ * - SDRAM 0x06000000 Size 16MByte mask 0xff000000
+ * - EPLD CFG 0x07000000 Size 512Bytes
+ * - FLASH 0x03000000 Size up to 8MByte
+ * - CPU 0x01000000 Size 4MByte (only accessable if special configured)
+ *
+ * Implemention:
+ * -------------
+ * To prevent using large resources reservation on the host following
+ * PCI mapping is choosed:
+ * - pci_cfg_mem_base: fixed address to the PLX config area size 512Bytes
+ * - pci_space0_addr: configured to the EPLD Config Area size 256Bytes
+ * - pci_space1_addr: configured to the SDRAM Area size 1MBytes, this
+ * space is used to switch between SDRAM, Flash and CPU
+ *
+ */
+
+/* Attribute definitions */
+#define PATI_BUS_SIZE_8 0
+#define PATI_BUS_SIZE_16 1
+#define PATI_BUS_SIZE_32 3
+
+#define PATI_SPACE0_MASK (0xFEFFFE00) /* Mask Attributes */
+#define PATI_SPACE1_MASK (0x00000000) /* Mask Attributes */
+
+#define PATI_EXTRA_LONG_EEPROM 1
+
+#define SPACE0_TA_ENABLE (1<<6)
+#define SPACE1_TA_ENABLE (1<<6)
+
+/* Config Area */
+#define PATI_LOC_CFG_ADDR 0x07000000 /* Local Address */
+#define PATI_LOC_CFG_MASK 0xFFFFFF00 /* 256 Bytes */
+/* Attributes */
+#define PATI_LOC_CFG_BUS_SIZE PATI_BUS_SIZE_32 /* 32 Bit */
+#define PATI_LOC_CFG_BURST 0 /* No Burst */
+#define PATI_LOC_CFG_NO_PREFETCH 1 /* No Prefetch */
+#define PATI_LOC_CFG_TA_ENABLE 1 /* Enable TA */
+
+#define PATI_LOC_CFG_SPACE0_ATTR ( \
+ PATI_LOC_CFG_BUS_SIZE | \
+ (PATI_LOC_CFG_TA_ENABLE << 6) | \
+ (PATI_LOC_CFG_NO_PREFETCH << 8) | \
+ (PATI_LOC_CFG_BURST << 24) | \
+ (PATI_EXTRA_LONG_EEPROM << 25))
+
+/* should never be used */
+#define PATI_LOC_CFG_SPACE1_ATTR ( \
+ PATI_LOC_CFG_BUS_SIZE | \
+ (PATI_LOC_CFG_TA_ENABLE << 6) | \
+ (PATI_LOC_CFG_NO_PREFETCH << 9) | \
+ (PATI_LOC_CFG_BURST << 8))
+
+
+/* SDRAM Area */
+#define PATI_LOC_SDRAM_ADDR 0x06000000 /* Local Address */
+#define PATI_LOC_SDRAM_MASK 0xFFF00000 /* 1MByte */
+/* Attributes */
+#define PATI_LOC_SDRAM_BUS_SIZE PATI_BUS_SIZE_32 /* 32 Bit */
+#define PATI_LOC_SDRAM_BURST 0 /* No Burst */
+#define PATI_LOC_SDRAM_NO_PREFETCH 0 /* Prefetch */
+#define PATI_LOC_SDRAM_TA_ENABLE 1 /* Enable TA */
+
+/* should never be used */
+#define PATI_LOC_SDRAM_SPACE0_ATTR ( \
+ PATI_LOC_SDRAM_BUS_SIZE | \
+ (PATI_LOC_SDRAM_TA_ENABLE << 6) | \
+ (PATI_LOC_SDRAM_NO_PREFETCH << 8) | \
+ (PATI_LOC_SDRAM_BURST << 24) | \
+ (PATI_EXTRA_LONG_EEPROM << 25))
+
+#define PATI_LOC_SDRAM_SPACE1_ATTR ( \
+ PATI_LOC_SDRAM_BUS_SIZE | \
+ (PATI_LOC_SDRAM_TA_ENABLE << 6) | \
+ (PATI_LOC_SDRAM_NO_PREFETCH << 9) | \
+ (PATI_LOC_SDRAM_BURST << 8))
+
+
+/* Flash Area */
+#define PATI_LOC_FLASH_ADDR 0x03000000 /* Local Address */
+#define PATI_LOC_FLASH_MASK 0xFFF00000 /* 1MByte */
+/* Attributes */
+#define PATI_LOC_FLASH_BUS_SIZE PATI_BUS_SIZE_16 /* 16 Bit */
+#define PATI_LOC_FLASH_BURST 0 /* No Burst */
+#define PATI_LOC_FLASH_NO_PREFETCH 1 /* No Prefetch */
+#define PATI_LOC_FLASH_TA_ENABLE 1 /* Enable TA */
+
+/* should never be used */
+#define PATI_LOC_FLASH_SPACE0_ATTR ( \
+ PATI_LOC_FLASH_BUS_SIZE | \
+ (PATI_LOC_FLASH_TA_ENABLE << 6) | \
+ (PATI_LOC_FLASH_NO_PREFETCH << 8) | \
+ (PATI_LOC_FLASH_BURST << 24) | \
+ (PATI_EXTRA_LONG_EEPROM << 25))
+
+#define PATI_LOC_FLASH_SPACE1_ATTR ( \
+ PATI_LOC_FLASH_BUS_SIZE | \
+ (PATI_LOC_FLASH_TA_ENABLE << 6) | \
+ (PATI_LOC_FLASH_NO_PREFETCH << 9) | \
+ (PATI_LOC_FLASH_BURST << 8))
+
+
+/* CPU Area */
+#define PATI_LOC_CPU_ADDR 0x01000000 /* Local Address */
+#define PATI_LOC_CPU_MASK 0xFFF00000 /* 1Mbyte */
+/* Attributes */
+#define PATI_LOC_CPU_BUS_SIZE PATI_BUS_SIZE_32 /* 32 Bit */
+#define PATI_LOC_CPU_BURST 0 /* No Burst */
+#define PATI_LOC_CPU_NO_PREFETCH 1 /* No Prefetch */
+#define PATI_LOC_CPU_TA_ENABLE 1 /* Enable TA */
+
+/* should never be used */
+#define PATI_LOC_CPU_SPACE0_ATTR ( \
+ PATI_LOC_CPU_BUS_SIZE | \
+ (PATI_LOC_CPU_TA_ENABLE << 6) | \
+ (PATI_LOC_CPU_NO_PREFETCH << 8) | \
+ (PATI_LOC_CPU_BURST << 24) | \
+ (PATI_EXTRA_CPU_EEPROM << 25))
+
+#define PATI_LOC_CPU_SPACE1_ATTR ( \
+ PATI_LOC_CPU_BUS_SIZE | \
+ (PATI_LOC_CPU_TA_ENABLE << 6) | \
+ (PATI_LOC_CPU_NO_PREFETCH << 9) | \
+ (PATI_LOC_CPU_BURST << 8))
+
+/***************************************************
+ * Hardware Config word definition
+ ***************************************************/
+#define BOOT_EXT_FLASH 0x00000000
+#define BOOT_INT_FLASH 0x00000004
+#define BOOT_FROM_PCI 0x00000006
+#define BOOT_FROM_SDRAM 0x00000005
+
+#define ENABLE_INT_ARB 0x00000008
+
+#define INITIAL_IRQ_PREF 0x00000010
+
+#define INITIAL_MEM_0M 0x00000000
+#define INITIAL_MEM_4M 0x00000080
+#define INITIAL_MEM_8M 0x00000040
+#define INITIAL_MEM_12M 0x000000C0
+#define INITIAL_MEM_16M 0x00000020
+#define INITIAL_MEM_20M 0x000000A0
+#define INITIAL_MEM_24M 0x00000060
+#define INITIAL_MEM_28M 0x000000E0
+/* CONF */
+#define INTERNAL_HWCONF 0x00000100
+/* PRPM */
+#define LOCAL_CPU_SLAVE 0x00000200
+/* BDIS */
+#define DISABLE_MEM_CNTR 0x00000400
+/* PCIM */
+#define PCI_MASTER_ONLY 0x00000800
+
+
+#define PATI_HW_START ((BOOT_EXT_FLASH | INITIAL_MEM_28M | INITIAL_IRQ_PREF))
+#define PATI_HW_PCI_ONLY ((BOOT_EXT_FLASH | INITIAL_MEM_28M | INITIAL_IRQ_PREF | PCI_MASTER_ONLY))
+#define PATI_HW_CPU_ACC ((BOOT_EXT_FLASH | INITIAL_MEM_12M | INITIAL_IRQ_PREF | PCI_MASTER_ONLY))
+#define PATI_HW_CPU_SLAVE ((BOOT_EXT_FLASH | INITIAL_MEM_12M | INITIAL_IRQ_PREF | PCI_MASTER_ONLY | LOCAL_CPU_SLAVE))
+
+/***************************************************
+ * Direct Master Config
+ ***************************************************/
+#define PATI_DMASTER_PCI_ADDR 0x01000000
+#define PATI_BUS_MASTER 1
+
+
+#define PATI_DMASTER_MASK 0xFFF00000 /* 1MByte */
+#define PATI_DMASTER_ADDR 0x01000000 /* Local Address */
+
+#define PATI_DMASTER_MEMORY_EN 0x00000001 /* 0x00000001 */
+#define PATI_DMASTER_READ_AHEAD 0x00000004 /* 0x00000004 */
+#define PATI_DMASTER_READ_NOT_AHEAD 0x00000000 /* 0x00000004 */
+#define PATI_DMASTER_PRE_SIZE_CNTRL_0 0x00000000
+#define PATI_DMASTER_PRE_SIZE_CNTRL_4 0x00000008
+#define PATI_DMASTER_PRE_SIZE_CNTRL_8 0x00001000
+#define PATI_DMASTER_PRE_SIZE_CNTRL_16 0x00001008
+#define PATI_DMASTER_REL_PCI 0x00000000
+#define PATI_DMASTER_NOT_REL_PCI 0x00000010
+#define PATI_DMASTER_WR_INVAL 0x00000200
+#define PATI_DMASTER_NOT_WR_INVAL 0x00000000
+#define PATI_DMASTER_PRE_LIMIT 0x00000800
+#define PATI_DMASTER_PRE_CONT 0x00000000
+#define PATI_DMASTER_DELAY_WR_0 0x00000000
+#define PATI_DMASTER_DELAY_WR_4 0x00004000
+#define PATI_DMASTER_DELAY_WR_8 0x00008000
+#define PATI_DMASTER_DELAY_WR_16 0x0000C000
+
+#define PATI_DMASTER_PCI_ADDR_MASK 0xFFFF0000
+
+#define PATI_DMASTER_ATTR \
+ PATI_DMASTER_MEMORY_EN | \
+ PATI_DMASTER_READ_AHEAD | \
+ PATI_DMASTER_PRE_SIZE_CNTRL_4 | \
+ PATI_DMASTER_REL_PCI | \
+ PATI_DMASTER_NOT_WR_INVAL | \
+ PATI_DMASTER_PRE_LIMIT | \
+ PATI_DMASTER_DELAY_WR_0
+
+
+#endif /* #ifndef __PATI_H_ */
diff --git a/board/mpl/pati/pci_eeprom.h b/board/mpl/pati/pci_eeprom.h
new file mode 100644
index 0000000000..459c14381d
--- /dev/null
+++ b/board/mpl/pati/pci_eeprom.h
@@ -0,0 +1,90 @@
+#ifndef __PCI_EEPROM_H_
+#define __PCI_EEPROM_H_ 1
+
+#include "pati.h"
+/******************************************************************************
+ * Eeprom Support
+ ******************************************************************************/
+/**********************************************
+* Definitions
+**********************************************/
+#define EE46_CMD_LEN 9 /* Bits in instructions */
+#define EE56_CMD_LEN 11 /* Bits in instructions */
+#define EE66_CMD_LEN 11 /* Bits in instructions */
+#define EE_READ 0x0180 /* 01 1000 0000 read instruction */
+#define EE_WRITE 0x0140 /* 01 0100 0000 write instruction */
+#define EE_WREN 0x0130 /* 01 0011 0000 write enable instruction */
+#define EE_WRALL 0x0110 /* 01 0001 0000 write all registers */
+#define EE_PRREAD 0x0180 /* 01 1000 0000 read address stored in Protect Register */
+#define EE_PRWRITE 0x0140 /* 01 0100 0000 write the address into PR */
+#define EE_WDS 0x0100 /* 01 0000 0000 write disable instruction */
+#define EE_PREN 0x0130 /* 01 0011 0000 protect enable instruction */
+#define EE_PRCLEAR 0x01FF /* 01 1111 1111 clear protect register instr */
+#define EE_PRDS 0x0100 /* 01 0000 0000 ONE TIME ONLY, permenant */
+
+/***************************************************
+ * EEPROM
+ ***************************************************/
+#define LOW_WORD(x) (((x) & 0xFFFF))
+#define HIGH_WORD(x) (((x) >> 16) & 0xFFFF)
+
+typedef struct pci_eeprom_t {
+ unsigned short offset;
+ unsigned short value;
+} pci_eeprom;
+
+static pci_eeprom pati_eeprom[] = {
+ { 0x00,PCI_DEVICE_ID_PATI }, /* PCI Device ID PCIIDR[31:16] */
+ { 0x02,PCI_VENDOR_ID_MPL }, /* PCI Vendor ID PCIIDR[15:0] */
+ { 0x04,PCI_CLASS_PROCESSOR_POWERPC }, /* PCI Class Code PCICCR[23:8] */
+ { 0x06,0x00BA }, /* PCI Class Code / PCI Revision ID PCICCR[7:0] / PCIREV[7:0] */
+ { 0x08,0x0007 }, /* PCI Maximum Latency / PCI Minimum Grant PCIMLR[7:0] / PCIMGR[7:0] */
+ { 0x0A,0x0100 }, /* PCI Interrupt Pin / PCI Interrupt Line PCIIPR[7:0] / PCIILR[7:0] */
+ { 0x0C,0x0000 }, /* MSW of Mailbox 0 (User Defined) PCI9056_MAILBOX0[31:16] */
+ { 0x0E,0x0000 }, /* LSW of Mailbox 0 (User Defined) PCI9056_MAILBOX0[15:0] */
+ { 0x10,0x0000 }, /* MSW of Mailbox 1 (User Defined) PCI9056_MAILBOX1[31:16] */
+ { 0x12,0x0000 }, /* LSW of Mailbox 1 (User Defined) PCI9056_MAILBOX1[15:0] */
+ { 0x14,HIGH_WORD(PATI_LOC_CFG_MASK) }, /* MSW of Direct Slave Local Address Space 0 Range LAS0RR[31:16] */
+ { 0x16,LOW_WORD(PATI_LOC_CFG_MASK) }, /* LSW of Direct Slave Local Address Space 0 Range LAS0RR[15:0] */
+ { 0x18,HIGH_WORD(PATI_LOC_CFG_ADDR) }, /* MSW of Direct Slave Local Address Space 0 Local Base Address (Remap) LAS0BA[31:16] (CFG) */
+ { 0x1A,LOW_WORD(PATI_LOC_CFG_ADDR)|1 }, /* LSW of Direct Slave Local Address Space 0 Local Base Address (Remap) LAS0BA[15:2, 0], Reserved [1] */
+ { 0x1C,0x0000 }, /* MSW of Mode/DMA Arbitration MARBR[31, 29:16] or DMAARB[31, 29:16], Reserved [30] */
+ { 0x1E,0x0000 }, /* LSW of Mode/DMA Arbitration MARBR[15:0] or DMAARB[15:0] */
+ { 0x20,0x0030 }, /* Local Miscellaneous Control 2 / Serial EEPROM WP Addr Boundary LMISC2[5:0], Res[7:6] / PROT_AREA[6:0], Res[7] */
+ { 0x22,0x0510 }, /* Local Miscellaneous Control 1 / Local Bus Big/Little Endian Descriptor LMISC1[7:0] / BIGEND[7:0] */
+ { 0x24,0x0000 }, /* MSW of Direct Slave Expansion ROM Range EROMRR[31:16] */
+ { 0x26,0x0000 }, /* LSW of Direct Slave Expansion ROM Range EROMRR[15:11, 0], Reserved [10:1] */
+ { 0x28,0x0000 }, /* MSW of Direct Slave Expansion ROM Local Base Address (Remap) and BREQo Control EROMBA[31:16] */
+ { 0x2A,0x0000 }, /* LSW of Direct Slave Expansion ROM Local Base Address (Remap) and BREQo Control EROMBA[15:11, 5:0], Reserved [10:6] */
+ { 0x2C,(0x4243 | HIGH_WORD((PATI_LOC_CFG_SPACE0_ATTR))) }, /* MSW of Local Address Space 0/Expansion ROM Bus Region Descriptor LBRD0[31:16] */
+ { 0x2E,LOW_WORD(PATI_LOC_CFG_SPACE0_ATTR) }, /* LSW of Local Address Space 0/Expansion ROM Bus Region Descriptor LBRD0[15:0] */
+ { 0x30,HIGH_WORD(PATI_DMASTER_MASK) }, /* MSW of Local Range for Direct Master-to-PCI DMRR[31:16] */
+ { 0x32,LOW_WORD(PATI_DMASTER_MASK) }, /* LSW of Local Range for Direct Master-to-PCI (Reserved) DMRR[15:0] */
+ { 0x34,HIGH_WORD(PATI_DMASTER_ADDR) }, /* MSW of Local Base Address for Direct Master-to-PCI Memory DMLBAM[31:16] */
+ { 0x36,LOW_WORD(PATI_DMASTER_ADDR) }, /* LSW of Local Base Address for Direct Master-to-PCI Memory (Reserved) DMLBAM[15:0] */
+ { 0x38,0x0000 }, /* MSW of Local Bus Address for Direct Master-to-PCI I/O Configuration DMLBAI[31:16] */
+ { 0x3A,0x0000 }, /* LSW of Local Bus Address for Direct Master-to-PCI I/O Configuration (Reserved) DMLBAI[15:0] */
+ { 0x3C,0x0000 }, /* MSW of PCI Base Address (Remap) for Direct Master-to-PCI Memory DMPBAM[31:16] */
+ { 0x3E,0x0000 }, /* LSW of PCI Base Address (Remap) for Direct Master-to-PCI Memory DMPBAM[15:0] */
+ { 0x40,0x0000 }, /* MSW of PCI Configuration Address for Direct Master-to-PCI I/O Configuration DMCFGA[31, 23:16] Reserved [30:24]*/
+ { 0x42,0x0000 }, /* LSW of PCI Configuration Address for Direct Master-to-PCI I/O Configuration DMCFGA[15:0] */
+ { 0x44,0x0000 }, /* PCI Subsystem ID PCISID[15:0] */
+ { 0x46,0x0000 }, /* PCI Subsystem Vendor ID PCISVID[15:0] */
+ { 0x48,HIGH_WORD(PATI_LOC_SDRAM_MASK) }, /* MSW of Direct Slave Local Address Space 1 Range (1 MB) LAS1RR[31:16] */
+ { 0x4A,LOW_WORD(PATI_LOC_SDRAM_MASK) }, /* LSW of Direct Slave Local Address Space 1 Range (1 MB) LAS1RR[15:0] */
+ { 0x4C,HIGH_WORD(PATI_LOC_SDRAM_ADDR) }, /* MSW of Direct Slave Local Address Space 1 Local Base Address (Remap) LAS1BA[31:16] (SDRAM) */
+ { 0x4E,LOW_WORD(PATI_LOC_SDRAM_ADDR) | 0x1 }, /* LSW of Direct Slave Local Address Space 1 Local Base Address (Remap) LAS1BA[15:2, 0], Reserved [1] */
+ { 0x50,HIGH_WORD(PATI_LOC_SDRAM_SPACE1_ATTR) }, /* MSW of Local Address Space 1 Bus Region Descriptor LBRD1[31:16] */
+ { 0x52,LOW_WORD(PATI_LOC_SDRAM_SPACE1_ATTR) }, /* LSW of Local Address Space 1 Bus Region Descriptor (Reserved) LBRD1[15:0] */
+ { 0x54,0x0000 }, /* Hot Swap Control/Status (Reserved) Reserved */
+ { 0x56,0x0000 }, /* Hot Swap Next Capability Pointer / Hot Swap Control HS_NEXT[7:0] / HS_CNTL[7:0] */
+ { 0x58,0x0000 }, /* Reserved Reserved */
+ { 0x5A,0x0000 }, /* PCI Arbiter Control PCIARB[3:0], Reserved [15:4] */
+ { 0x5C,0x0000 }, /* Power Management Capabilities PMC[15:9, 2:0] */
+ { 0x5E,0x0000 }, /* Power Management Next Capability Pointer (Reserved) / Power Management Capability ID (Reserved) Reserved*/
+ { 0x60,0x0000 }, /* Power Management Data / PMCSR Bridge Support Extension (Reserved) PMDATA[7:0] / Reserved */
+ { 0x62,0x0000 }, /* Power Management Control/Status PMCSR[14:8] */
+ { 0xFFFF,0xFFFF} /* terminaror */
+};
+#define PATI_EEPROM_LAST_OFFSET 0x64
+#endif /* #ifndef __PCI_EEPROM_H_ */
diff --git a/board/mpl/pati/plx9056.h b/board/mpl/pati/plx9056.h
new file mode 100644
index 0000000000..754e72098e
--- /dev/null
+++ b/board/mpl/pati/plx9056.h
@@ -0,0 +1,95 @@
+/*
+ * (C) Copyright 2003
+ * Denis Peter, d.peter at mpl.ch
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+/* PLX9096 register definitions
+*/
+#ifndef __PLX9056_H_
+#define __PLX9056_H_ 1
+
+#include <pci.h>
+
+#ifdef PLX9056_LOC
+#define LOCAL_OFFSET 0x080
+/* PCI Config regs */
+#else
+#define LOCAL_OFFSET 0x000
+#endif
+
+#define PCI9056_VENDOR_ID PCI_VENDOR_ID
+/*#define PCI9656_DEVICE_ID PCI_DEVICE_ID */
+#define PCI9056_COMMAND PCI_COMMAND
+/*#define PCI9656_STATUS PCI_STATUS */
+#define PCI9056_REVISION PCI_REVISION_ID
+
+#define PCI9056_CACHE_SIZE PCI_CACHE_LINE_SIZE
+#define PCI9056_RTR_BASE PCI_BASE_ADDRESS_0
+#define PCI9056_RTR_IO_BASE PCI_BASE_ADDRESS_1
+#define PCI9056_LOCAL_BASE0 PCI_BASE_ADDRESS_2
+#define PCI9056_LOCAL_BASE1 PCI_BASE_ADDRESS_3
+#define PCI9056_UNUSED_BASE1 PCI_BASE_ADDRESS_4
+#define PCI9056_UNUSED_BASE2 PCI_BASE_ADDRESS_5
+#define PCI9056_CIS_PTR PCI_CARDBUS_CIS
+#define PCI9056_SUB_ID PCI_SUBSYSTEM_VENDOR_ID
+#define PCI9056_EXP_ROM_BASE PCI_ROM_ADDRESS
+#define PCI9056_CAP_PTR PCI_CAPABILITY_LIST
+#define PCI9056_INT_LINE PCI_INTERRUPT_LINE
+
+#if defined(PLX9056_LOC)
+ #define PCI9056_PM_CAP_ID 0x180
+ #define PCI9056_PM_CSR 0x184
+ #define PCI9056_HS_CAP_ID 0x188
+ #define PCI9056_VPD_CAP_ID 0x18C
+ #define PCI9056_VPD_DATA 0x190
+#endif
+
+
+#define PCI_DEVICE_ID_PLX9056 0x9056
+
+/* Local Configuration Registers Accessible via the PCI Base address + Variable */
+#define PCI9056_SPACE0_RANGE (0x000 + LOCAL_OFFSET)
+#define PCI9056_SPACE0_REMAP (0x004 + LOCAL_OFFSET)
+#define PCI9056_LOCAL_DMA_ARBIT (0x008 + LOCAL_OFFSET)
+#define PCI9056_ENDIAN_DESC (0x00c + LOCAL_OFFSET)
+#define PCI9056_EXP_ROM_RANGE (0x010 + LOCAL_OFFSET)
+#define PCI9056_EXP_ROM_REMAP (0x014 + LOCAL_OFFSET)
+#define PCI9056_SPACE0_ROM_DESC (0x018 + LOCAL_OFFSET)
+#define PCI9056_DM_RANGE (0x01c + LOCAL_OFFSET)
+#define PCI9056_DM_MEM_BASE (0x020 + LOCAL_OFFSET)
+#define PCI9056_DM_IO_BASE (0x024 + LOCAL_OFFSET)
+#define PCI9056_DM_PCI_MEM_REMAP (0x028 + LOCAL_OFFSET)
+#define PCI9056_DM_PCI_IO_CONFIG (0x02c + LOCAL_OFFSET)
+#define PCI9056_SPACE1_RANGE (0x0f0 + LOCAL_OFFSET)
+#define PCI9056_SPACE1_REMAP (0x0f4 + LOCAL_OFFSET)
+#define PCI9056_SPACE1_DESC (0x0f8 + LOCAL_OFFSET)
+#define PCI9056_DM_DAC (0x0fc + LOCAL_OFFSET)
+
+#ifdef PLX9056_LOC
+#define PCI9056_ARBITER_CTRL 0x1A0
+#define PCI9056_ABORT_ADDRESS 0x1A4
+#endif
+
+/* Runtime registers PCI Address + LOCAL_OFFSET */
+#ifdef PLX9056_LOC
+#define PCI9056_MAILBOX0 0x0C0
+#define PCI9056_MAILBOX1 0x0C4
+#else
+#define PCI9056_MAILBOX0 0x078
+#define PCI9056_MAILBOX1 0x07c
+#endif
+
+#define PCI9056_MAILBOX2 (0x048 + LOCAL_OFFSET)
+#define PCI9056_MAILBOX3 (0x04c + LOCAL_OFFSET)
+#define PCI9056_MAILBOX4 (0x050 + LOCAL_OFFSET)
+#define PCI9056_MAILBOX5 (0x054 + LOCAL_OFFSET)
+#define PCI9056_MAILBOX6 (0x058 + LOCAL_OFFSET)
+#define PCI9056_MAILBOX7 (0x05c + LOCAL_OFFSET)
+#define PCI9056_PCI_TO_LOC_DBELL (0x060 + LOCAL_OFFSET)
+#define PCI9056_LOC_TO_PCI_DBELL (0x064 + LOCAL_OFFSET)
+#define PCI9056_INT_CTRL_STAT (0x068 + LOCAL_OFFSET)
+#define PCI9056_EEPROM_CTRL_STAT (0x06c + LOCAL_OFFSET)
+#define PCI9056_PERM_VENDOR_ID (0x070 + LOCAL_OFFSET)
+#define PCI9056_REVISION_ID (0x074 + LOCAL_OFFSET)
+
+#endif /* #ifndef __PLX9056_H_ */
diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c
index 48dba20936..81967ff5b4 100644
--- a/cmd/bdinfo.c
+++ b/cmd/bdinfo.c
@@ -183,7 +183,8 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
print_bi_flash(bd);
print_num("sramstart", bd->bi_sramstart);
print_num("sramsize", bd->bi_sramsize);
-#if defined(CONFIG_E500)
+#if defined(CONFIG_5xx) || \
+ defined(CONFIG_E500)
print_num("immr_base", bd->bi_immr_base);
#endif
print_num("bootflags", bd->bi_bootflags);
diff --git a/cmd/reginfo.c b/cmd/reginfo.c
index 6918a9edf5..d971a8fd80 100644
--- a/cmd/reginfo.c
+++ b/cmd/reginfo.c
@@ -9,6 +9,8 @@
#include <command.h>
#if defined (CONFIG_4xx)
extern void ppc4xx_reginfo(void);
+#elif defined (CONFIG_5xx)
+#include <mpc5xx.h>
#elif defined (CONFIG_MPC5200)
#include <mpc5xxx.h>
#elif defined (CONFIG_MPC86xx)
@@ -22,6 +24,41 @@ static int do_reginfo(cmd_tbl_t *cmdtp, int flag, int argc,
{
#if defined (CONFIG_4xx)
ppc4xx_reginfo();
+#elif defined(CONFIG_5xx)
+
+ volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
+ volatile memctl5xx_t *memctl = &immap->im_memctl;
+ volatile sysconf5xx_t *sysconf = &immap->im_siu_conf;
+ volatile sit5xx_t *timers = &immap->im_sit;
+ volatile car5xx_t *car = &immap->im_clkrst;
+ volatile uimb5xx_t *uimb = &immap->im_uimb;
+
+ puts ("\nSystem Configuration registers\n");
+ printf("\tIMMR\t0x%08X\tSIUMCR\t0x%08X \n", get_immr(0), sysconf->sc_siumcr);
+ printf("\tSYPCR\t0x%08X\tSWSR\t0x%04X \n" ,sysconf->sc_sypcr, sysconf->sc_swsr);
+ printf("\tSIPEND\t0x%08X\tSIMASK\t0x%08X \n", sysconf->sc_sipend, sysconf->sc_simask);
+ printf("\tSIEL\t0x%08X\tSIVEC\t0x%08X \n", sysconf->sc_siel, sysconf->sc_sivec);
+ printf("\tTESR\t0x%08X\n", sysconf->sc_tesr);
+
+ puts ("\nMemory Controller Registers\n");
+ printf("\tBR0\t0x%08X\tOR0\t0x%08X \n", memctl->memc_br0, memctl->memc_or0);
+ printf("\tBR1\t0x%08X\tOR1\t0x%08X \n", memctl->memc_br1, memctl->memc_or1);
+ printf("\tBR2\t0x%08X\tOR2\t0x%08X \n", memctl->memc_br2, memctl->memc_or2);
+ printf("\tBR3\t0x%08X\tOR3\t0x%08X \n", memctl->memc_br3, memctl->memc_or3);
+ printf("\tDMBR\t0x%08X\tDMOR\t0x%08X \n", memctl->memc_dmbr, memctl->memc_dmor );
+ printf("\tMSTAT\t0x%08X\n", memctl->memc_mstat);
+
+ puts ("\nSystem Integration Timers\n");
+ printf("\tTBSCR\t0x%08X\tRTCSC\t0x%08X \n", timers->sit_tbscr, timers->sit_rtcsc);
+ printf("\tPISCR\t0x%08X \n", timers->sit_piscr);
+
+ puts ("\nClocks and Reset\n");
+ printf("\tSCCR\t0x%08X\tPLPRCR\t0x%08X \n", car->car_sccr, car->car_plprcr);
+
+ puts ("\nU-Bus to IMB3 Bus Interface\n");
+ printf("\tUMCR\t0x%08X\tUIPEND\t0x%08X \n", uimb->uimb_umcr, uimb->uimb_uipend);
+ puts ("\n\n");
+
#elif defined(CONFIG_MPC5200)
puts ("\nMPC5200 registers\n");
printf ("MBAR=%08x\n", CONFIG_SYS_MBAR);
diff --git a/common/board_f.c b/common/board_f.c
index 8bf9acca48..e1ec284d75 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -547,7 +547,8 @@ static int setup_board_part1(void)
bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM */
#endif
-#if defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
+#if defined(CONFIG_5xx) || \
+ defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
bd->bi_immr_base = CONFIG_SYS_IMMR; /* base of IMMR register */
#endif
#if defined(CONFIG_MPC5xxx) || defined(CONFIG_M68K)
diff --git a/configs/PATI_defconfig b/configs/PATI_defconfig
new file mode 100644
index 0000000000..cd78de7b4b
--- /dev/null
+++ b/configs/PATI_defconfig
@@ -0,0 +1,28 @@
+CONFIG_PPC=y
+CONFIG_IDENT_STRING="\n(c) 2003 by MPL AG Switzerland, MEV-10084-001 released"
+CONFIG_5xx=y
+CONFIG_TARGET_PATI=y
+CONFIG_BOOTDELAY=5
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SYS_PROMPT="pati=> "
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+CONFIG_CMD_EEPROM=y
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_ECHO is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_CMD_BSP=y
+CONFIG_CMD_IRQ=y
+# CONFIG_MMC is not set
+CONFIG_MTD_NOR_FLASH=y
+# CONFIG_PCI is not set
+CONFIG_BAUDRATE=9600
diff --git a/doc/README.mpc5xx b/doc/README.mpc5xx
new file mode 100644
index 0000000000..df51b5cf5c
--- /dev/null
+++ b/doc/README.mpc5xx
@@ -0,0 +1,48 @@
+
+Summary:
+========
+
+This file contains information about the port of U-Boot to the
+Motorola mpc5xx series of CPUs. Most of this code is taken from
+existing code mainly from the mpc8xx port. In contrast to mpc8xx,
+the mpc5xx has no CPM, MMU and cache facilities.
+
+The implemented features have been tested on the cmi board, a
+customer specific board (see README.cmi).
+
+Hence this port is only tested on the cmi board further possible
+tests on other boards will be very valuable.
+
+Not Tested Features:
+====================
+
+* System calls
+* Interrupts
+
+Added or Changed Files:
+=======================
+
+u-boot-0.2.0/common/cmd_boot.c
+u-boot-0.2.0/common/cmd_reginfo.c
+u-boot-0.2.0/common/environment.c
+u-boot-0.2.0/arch/powerpc/cpu/mpc5xx/*
+u-boot-0.2.0/include/cmd_reginfo.h
+u-boot-0.2.0/include/common.h
+u-boot-0.2.0/include/ppc_asm.tmpl
+u-boot-0.2.0/include/watchdog.h
+u-boot-0.2.0/include/mpc5xx.h
+u-boot-0.2.0/include/status_led.h
+u-boot-0.2.0/include/asm-ppc/u-boot.h
+u-boot-0.2.0/include/asm-ppc/5xx_immap.h
+u-boot-0.2.0/arch/powerpc/lib/board.c
+u-boot-0.2.0/arch/powerpc/lib/cache.c
+u-boot-0.2.0/arch/powerpc/lib/time.c
+u-boot-0.2.0/Makefile
+u-boot-0.2.0/CREDITS
+u-boot-0.2.0/doc/README.mpc5xx
+u-boot-0.2.0/doc/README.cmi
+u-boot-0.2.0/README
+u-boot-0.2.0/MAKEALL
+
+Regards,
+Martin
diff --git a/include/asm-generic/u-boot.h b/include/asm-generic/u-boot.h
index 0c1bdc77d9..a7797137f3 100644
--- a/include/asm-generic/u-boot.h
+++ b/include/asm-generic/u-boot.h
@@ -41,7 +41,8 @@ typedef struct bd_info {
unsigned long bi_dsp_freq; /* dsp core frequency */
unsigned long bi_ddr_freq; /* ddr frequency */
#endif
-#if defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
+#if defined(CONFIG_5xx) \
+ || defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
unsigned long bi_immr_base; /* base of IMMR register */
#endif
#if defined(CONFIG_MPC5xxx) || defined(CONFIG_M68K)
diff --git a/include/configs/PATI.h b/include/configs/PATI.h
new file mode 100644
index 0000000000..1f26ac4c2d
--- /dev/null
+++ b/include/configs/PATI.h
@@ -0,0 +1,245 @@
+/*
+ * (C) Copyright 2003
+ * Denis Peter d.peter at mpl.ch
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * File: PATI.h
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+
+#define CONFIG_MPC555 1 /* This is an MPC555 CPU */
+#define CONFIG_PATI 1 /* ...On a PATI board */
+
+#define CONFIG_SYS_TEXT_BASE 0xFFF00000
+
+/* Serial Console Configuration */
+#define CONFIG_5xx_CONS_SCI1
+#undef CONFIG_5xx_CONS_SCI2
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_REGINFO
+
+#define CONFIG_BOOTCOMMAND "" /* autoboot command */
+
+#define CONFIG_BOOTARGS "" /* */
+
+#define CONFIG_WATCHDOG /* turn on platform specific watchdog */
+
+#define CONFIG_LOADS_ECHO 1 /* Echo on for serial download */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_PREBOOT
+
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+
+#define CONFIG_SYS_MEMTEST_START 0x00010000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0x00A00000 /* 10 MB in SRAM */
+
+#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
+
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 1250000 }
+
+/***********************************************************************
+ * Last Stage Init
+ ***********************************************************************/
+#define CONFIG_LAST_STAGE_INIT
+
+/*
+ * Low Level Configuration Settings
+ */
+
+/*
+ * Internal Memory Mapped (This is not the IMMR content)
+ */
+#define CONFIG_SYS_IMMR 0x01C00000 /* Physical start adress of internal memory map */
+
+/*
+ * Definitions for initial stack pointer and data area
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_IMMR + 0x003f9800) /* Physical start adress of internal MPC555 writable RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE (CONFIG_SYS_IMMR + 0x003fffff) /* Physical end adress of internal MPC555 used RAM area */
+#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_INIT_RAM_ADDR) - GENERATED_GBL_DATA_SIZE) /* Offset from the beginning of ram */
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_IMMR + 0x03fa000) /* Physical start adress of inital stack */
+/*
+ * Start addresses for the final memory configuration
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* Monitor won't change memory map */
+#define CONFIG_SYS_FLASH_BASE 0xffC00000 /* External flash */
+#define PCI_BASE 0x03000000 /* PCI Base (CS2) */
+#define PCI_CONFIG_BASE 0x04000000 /* PCI & PLD (CS3) */
+#define PLD_CONFIG_BASE 0x04001000 /* PLD (CS3) */
+
+#define CONFIG_SYS_MONITOR_BASE 0xFFF00000
+/* CONFIG_SYS_FLASH_BASE */ /* CONFIG_SYS_TEXT_BASE is defined in the board config.mk file. */
+ /* This adress is given to the linker with -Ttext to */
+ /* locate the text section at this adress. */
+#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 192 kB for Monitor */
+#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
+
+#define CONFIG_SYS_RESET_ADDRESS (PLD_CONFIG_BASE + 0x10) /* Adress which causes reset */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ *-----------------------------------------------------------------------
+ *
+ */
+
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+
+#define CONFIG_FLASH_SHOW_PROGRESS 45
+
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define CONFIG_SYS_MAX_FLASH_SECT 128
+
+#define CONFIG_ENV_IS_IN_EEPROM
+#ifdef CONFIG_ENV_IS_IN_EEPROM
+#define CONFIG_ENV_OFFSET 0
+#define CONFIG_ENV_SIZE 2048
+#endif
+
+#undef CONFIG_ENV_IS_IN_FLASH
+#ifdef CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SIZE 0x00002000 /* Set whole sector as env */
+#define CONFIG_ENV_OFFSET ((0 - CONFIG_SYS_FLASH_BASE) - CONFIG_ENV_SIZE) /* Environment starts at this adress */
+#endif
+
+#define CONFIG_SPI 1
+#define CONFIG_SYS_SPI_CS_USED 0x09 /* CS0 and CS3 are used */
+#define CONFIG_SYS_SPI_CS_BASE 0x08 /* CS3 is active low */
+#define CONFIG_SYS_SPI_CS_ACT 0x00 /* CS3 is active low */
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * SW Watchdog freeze
+ */
+#undef CONFIG_WATCHDOG
+#if defined(CONFIG_WATCHDOG)
+#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+ SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+ SYPCR_SWP)
+#endif /* CONFIG_WATCHDOG */
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK SCCR_EBDF00
+#define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_RTDIV | SCCR_RTSEL | \
+ SCCR_COM01 | SCCR_DFNL000 | SCCR_DFNH000)
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration
+ *-----------------------------------------------------------------------
+ * Data show cycle
+ */
+#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_EARB | SIUMCR_GPC01 | SIUMCR_MLRC11) /* Disable data show cycle */
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register
+ *-----------------------------------------------------------------------
+ * Set all bits to 40 Mhz
+ *
+ */
+#define CONFIG_SYS_OSC_CLK ((uint)4000000) /* Oscillator clock is 4MHz */
+
+#define CONFIG_SYS_PLPRCR (PLPRCR_MF_9 | PLPRCR_DIVF_0)
+
+/*-----------------------------------------------------------------------
+ * UMCR - UIMB Module Configuration Register
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CONFIG_SYS_UMCR (UMCR_FSPEED) /* IMB clock same as U-bus */
+
+/*-----------------------------------------------------------------------
+ * ICTRL - I-Bus Support Control Register
+ */
+#define CONFIG_SYS_ICTRL (ICTRL_ISCT_SER_7) /* Take out of serialized mode */
+
+/*-----------------------------------------------------------------------
+ * USIU - Memory Controller Register
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BR_V | BR_BI | BR_PS_16 | BR_SETA)
+#define CONFIG_SYS_OR0_PRELIM (0xffc00000) /* SCY is not used if external TA is set */
+/* SDRAM */
+#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_SDRAM_BASE | BR_V | BR_BI | BR_PS_32 | BR_SETA)
+#define CONFIG_SYS_OR1_PRELIM (OR_ADDR_MK_FF) /* SCY is not used if external TA is set */
+/* PCI */
+#define CONFIG_SYS_BR2_PRELIM (PCI_BASE | BR_V | BR_PS_32 | BR_SETA)
+#define CONFIG_SYS_OR2_PRELIM (OR_ADDR_MK_FF)
+/* config registers: */
+#define CONFIG_SYS_BR3_PRELIM (PCI_CONFIG_BASE | BR_V | BR_BI | BR_PS_32 | BR_SETA)
+#define CONFIG_SYS_OR3_PRELIM (0xffff0000)
+
+#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* We don't realign the flash */
+
+/*-----------------------------------------------------------------------
+ * DER - Timer Decrementer
+ *-----------------------------------------------------------------------
+ * Initialise to zero
+ */
+#define CONFIG_SYS_DER 0x00000000
+
+#endif /* __CONFIG_H */
diff --git a/include/mpc5xx.h b/include/mpc5xx.h
new file mode 100644
index 0000000000..6c170dcb0a
--- /dev/null
+++ b/include/mpc5xx.h
@@ -0,0 +1,173 @@
+/*
+ * (C) Copyright 2003
+ * Martin Winistoerfer, martinwinistoerfer at gmx.ch.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * File: mpc5xx.h
+ *
+ * Discription: mpc5xx specific definitions
+ *
+ */
+
+#ifndef __MPC5XX_H__
+#define __MPC5XX_H__
+
+
+/*-----------------------------------------------------------------------
+ * Exception offsets (PowerPC standard)
+ */
+#define EXC_OFF_SYS_RESET 0x0100 /* System reset */
+#define _START_OFFSET EXC_OFF_SYS_RESET
+
+/*-----------------------------------------------------------------------
+ * ISB bit in IMMR to set internal memory map
+ */
+
+#define CONFIG_SYS_ISB ((CONFIG_SYS_IMMR / 0x00400000) << 1)
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control Register
+ */
+#define SYPCR_SWTC 0xffff0000 /* Software Watchdog Timer Count */
+#define SYPCR_BMT 0x0000ff00 /* Bus Monitor Timing */
+#define SYPCR_BME 0x00000080 /* Bus Monitor Enable */
+#define SYPCR_SWF 0x00000008 /* Software Watchdog Freeze */
+#define SYPCR_SWE 0x00000004 /* Software Watchdog Enable */
+#define SYPCR_SWRI 0x00000002 /* Software Watchdog Reset/Int Select */
+#define SYPCR_SWP 0x00000001 /* Software Watchdog Prescale */
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration Register
+ */
+#define SIUMCR_EARB 0x80000000 /* External Arbitration */
+#define SIUMCR_EARP0 0x00000000 /* External Arbi. Request priority 0 */
+#define SIUMCR_EARP1 0x10000000 /* External Arbi. Request priority 1 */
+#define SIUMCR_EARP2 0x20000000 /* External Arbi. Request priority 2 */
+#define SIUMCR_EARP3 0x30000000 /* External Arbi. Request priority 3 */
+#define SIUMCR_EARP4 0x40000000 /* External Arbi. Request priority 4 */
+#define SIUMCR_EARP5 0x50000000 /* External Arbi. Request priority 5 */
+#define SIUMCR_EARP6 0x60000000 /* External Arbi. Request priority 6 */
+#define SIUMCR_EARP7 0x70000000 /* External Arbi. Request priority 7 */
+#define SIUMCR_DSHW 0x00800000 /* Data Showcycles */
+#define SIUMCR_DBGC00 0x00000000 /* Debug pins configuration */
+#define SIUMCR_DBGC01 0x00200000 /* - " - */
+#define SIUMCR_DBGC10 0x00400000 /* - " - */
+#define SIUMCR_DBGC11 0x00600000 /* - " - */
+#define SIUMCR_DBPC00 0x00000000 /* Debug Port pins Config. */
+#define SIUMCR_DBPC01 0x00080000 /* - " - */
+#define SIUMCR_DBPC10 0x00100000 /* - " - */
+#define SIUMCR_DBPC11 0x00180000 /* - " - */
+#define SIUMCR_GPC00 0x00000000 /* General Pins Config */
+#define SIUMCR_GPC01 0x00020000 /* General Pins Config */
+#define SIUMCR_GPC10 0x00040000 /* General Pins Config */
+#define SIUMCR_GPC11 0x00060000 /* General Pins Config */
+#define SIUMCR_DLK 0x00010000 /* Debug Register Lock */
+#define SIUMCR_SC00 0x00000000 /* Multi Chip 32 bit */
+#define SIUMCR_SC01 0x00004000 /* Muilt Chip 16 bit */
+#define SIUMCR_SC10 0x00004000 /* Single adress show */
+#define SIUMCR_SC11 0x00006000 /* Single adress */
+#define SIUMCR_RCTX 0x00001000 /* Data Parity pins Config. */
+#define SIUMCR_MLRC00 0x00000000 /* Multi Level Reserva. Ctrl */
+#define SIUMCR_MLRC01 0x00000400 /* - " - */
+#define SIUMCR_MLRC10 0x00000800 /* - " - */
+#define SIUMCR_MLRC11 0x00000c00 /* - " - */
+#define SIUMCR_MTSC 0x00000100 /* Memory transfer */
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control Register
+ */
+#define TBSCR_REFA ((ushort)0x0080) /* Reference Interrupt Status A */
+#define TBSCR_REFB ((ushort)0x0040) /* Reference Interrupt Status B */
+#define TBSCR_TBF ((ushort)0x0002) /* Time Base stops while FREEZE */
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control Register
+ */
+#define PISCR_PITF ((ushort)0x0002) /* PIT stops when FREEZE */
+#define PISCR_PS 0x0080 /* Periodic Interrupt Status */
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register
+ */
+#define PLPRCR_MF_MSK 0xfff00000 /* MF mask */
+#define PLPRCR_DIVF_MSK 0x0000001f /* DIVF mask */
+#define PLPRCR_CSRC_MSK 0x00000400 /* CSRC mask */
+#define PLPRCR_MF_SHIFT 0x00000014 /* Multiplication factor shift value */
+#define PLPRCR_DIVF_0 0x00000000 /* Division factor 0 */
+#define PLPRCR_MF_9 0x00900000 /* Mulitipliaction factor 9 */
+#define PLPRCR_TEXPS 0x00004000 /* TEXP Status */
+#define PLPRCR_TMIST 0x00001000 /* Timers Interrupt Status */
+#define PLPRCR_CSR 0x00000080 /* CheskStop Reset value */
+#define PLPRCR_SPLSS 0x00008000 /* SPLL Lock Status Sticky bit */
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register
+ */
+#define SCCR_DFNL_MSK 0x00000070 /* DFNL mask */
+#define SCCR_DFNH_MSK 0x00000007 /* DFNH mask */
+#define SCCR_DFNL_SHIFT 0x0000004 /* DFNL shift value */
+#define SCCR_RTSEL 0x00100000 /* RTC circuit input source select */
+#define SCCR_EBDF00 0x00000000 /* Division factor 1. CLKOUT is GCLK2 */
+#define SCCR_EBDF11 0x00060000 /* reserved */
+#define SCCR_TBS 0x02000000 /* Time Base Source */
+#define SCCR_RTDIV 0x01000000 /* RTC Clock Divide */
+#define SCCR_COM00 0x00000000 /* full strength CLKOUT output buffer */
+#define SCCR_COM01 0x20000000 /* half strength CLKOUT output buffer */
+#define SCCR_DFNL000 0x00000000 /* Division by 2 (default = minimum) */
+#define SCCR_DFNH000 0x00000000 /* Division by 1 (default = minimum) */
+
+/*-----------------------------------------------------------------------
+ * MC - Memory Controller
+ */
+#define BR_V 0x00000001 /* Bank valid */
+#define BR_BI 0x00000002 /* Burst inhibit */
+#define BR_PS_8 0x00000400 /* 8 bit port size */
+#define BR_PS_16 0x00000800 /* 16 bit port size */
+#define BR_PS_32 0x00000000 /* 32 bit port size */
+#define BR_LBDIR 0x00000008 /* Late burst data in progess */
+#define BR_SETA 0x00000004 /* External Data Acknowledge */
+#define OR_SCY_3 0x00000030 /* 3 clock cycles wait states */
+#define OR_SCY_1 0x00000000 /* 1 clock cycle wait state */
+#define OR_SCY_8 0x00000080 /* 8 clock cycles wait states */
+#define OR_TRLX 0x00000001 /* Timing relaxed */
+#define OR_BSCY 0x00000060 /* Burst beats length in clocks */
+#define OR_ACS_10 0x00000600 /* Adress to chip-select setup */
+#define OR_CSNT 0x00000800 /* Chip-select negotation time */
+#define OR_ETHR 0x00000100 /* Extended hold time on read */
+#define OR_ADDR_MK_FF 0xFF000000
+#define OR_ADDR_MK_FFFF 0xFFFF0000
+
+/*-----------------------------------------------------------------------
+ * UMCR - UIMB Module Configuration Register
+ */
+#define UMCR_FSPEED 0x00000000 /* Full speed. Opposit of UMCR_HSPEED */
+#define UMCR_HSPEED 0x10000000 /* Half speed */
+
+/*-----------------------------------------------------------------------
+ * ICTRL - I-Bus Support Control Register
+ */
+#define ICTRL_ISCT_SER_7 0x00000007 /* All indirect change of flow */
+
+
+#define NR_IRQS 0 /* Place this later in a separate file */
+
+/*-----------------------------------------------------------------------
+ * SCI - Serial communication interface
+ */
+
+#define SCI_TDRE 0x0100 /* Transmit data register empty */
+#define SCI_TE 0x0008 /* Transmitter enabled */
+#define SCI_RE 0x0004 /* Receiver enabled */
+#define SCI_RDRF 0x0040 /* Receive data register full */
+#define SCI_PE 0x0400 /* Parity enable */
+#define SCI_SCXBR_MK 0x1fff /* Baudrate mask */
+#define SCI_SCXDR_MK 0x00ff /* Data register mask */
+#define SCI_M_11 0x0200 /* Frame size is 11 bit */
+#define SCI_M_10 0x0000 /* Frame size is 10 bit */
+#define SCI_PORT_1 ((int)1) /* Place this later somewhere better */
+#define SCI_PORT_2 ((int)2)
+
+#endif /* __MPC5XX_H__ */
diff --git a/include/ppc_asm.tmpl b/include/ppc_asm.tmpl
index 5a0fda212d..53141b1f71 100644
--- a/include/ppc_asm.tmpl
+++ b/include/ppc_asm.tmpl
@@ -81,6 +81,18 @@
#define r30 30
#define r31 31
+
+#if defined(CONFIG_5xx)
+/* Some special purpose registers */
+#define DER 149 /* Debug Enable Register */
+#define COUNTA 150 /* Breakpoint Counter */
+#define COUNTB 151 /* Breakpoint Counter */
+#define LCTRL1 156 /* Load/Store Support */
+#define LCTRL2 157 /* Load/Store Support */
+#define ICTRL 158 /* I-Bus Support Control Register */
+#define EID 81
+#endif /* CONFIG_5xx */
+
#if defined(CONFIG_MPC5xxx)
#define HID0_ICE_BITPOS 16
diff --git a/include/watchdog.h b/include/watchdog.h
index 20ac59a8b0..0055a837c3 100644
--- a/include/watchdog.h
+++ b/include/watchdog.h
@@ -72,6 +72,11 @@ int init_func_watchdog_reset(void);
* Prototypes from $(CPU)/cpu.c.
*/
+/* MPC 5xx */
+#if defined(CONFIG_5xx) && !defined(__ASSEMBLY__)
+ void reset_5xx_watchdog(volatile immap_t *immr);
+#endif
+
/* MPC 5xxx */
#if defined(CONFIG_MPC5xxx) && !defined(__ASSEMBLY__)
void reset_5xxx_watchdog(void);
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index f729e2bd54..c8caf98790 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -30,6 +30,9 @@ CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET
CONFIG_4xx_DCACHE
CONFIG_521X
CONFIG_533MHZ_MODE
+CONFIG_5xx_CONS_SCI1
+CONFIG_5xx_CONS_SCI2
+CONFIG_5xx_GCLK_FREQ
CONFIG_64BIT_PHYS_ADDR
CONFIG_66
CONFIG_8349_CLKIN
@@ -1653,6 +1656,7 @@ CONFIG_MPC5121ADS_REV2
CONFIG_MPC512x_FEC
CONFIG_MPC5200
CONFIG_MPC5200_DDR
+CONFIG_MPC555
CONFIG_MPC5xxx_FEC
CONFIG_MPC5xxx_FEC_MII10
CONFIG_MPC5xxx_FEC_MII100
@@ -1888,6 +1892,7 @@ CONFIG_PALMAS_SMPS7_FPWM
CONFIG_PALMAS_USB_SS_PWR
CONFIG_PANIC_HANG
CONFIG_PARAVIRT
+CONFIG_PATI
CONFIG_PB1000
CONFIG_PB1100
CONFIG_PB1500
@@ -3269,6 +3274,7 @@ CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
CONFIG_SYS_DEFAULT_MBAR
CONFIG_SYS_DEFAULT_VIDEO_MODE
CONFIG_SYS_DEF_EEPROM_ADDR
+CONFIG_SYS_DER
CONFIG_SYS_DEVICE_NULLDEV
CONFIG_SYS_DFU_DATA_BUF_SIZE
CONFIG_SYS_DFU_MAX_FILE_SIZE
@@ -4298,6 +4304,7 @@ CONFIG_SYS_ISA_IO_BASE_ADDRESS
CONFIG_SYS_ISA_IO_OFFSET
CONFIG_SYS_ISA_IO_STRIDE
CONFIG_SYS_ISA_MEM
+CONFIG_SYS_ISB
CONFIG_SYS_ISRAM_BASE
CONFIG_SYS_IVM_EEPROM_ADR
CONFIG_SYS_IVM_EEPROM_MAX_LEN
@@ -4453,6 +4460,7 @@ CONFIG_SYS_MARUBUN_IO
CONFIG_SYS_MARUBUN_MRSHPC
CONFIG_SYS_MARUBUN_MW1
CONFIG_SYS_MARUBUN_MW2
+CONFIG_SYS_MASK
CONFIG_SYS_MASTER_CLOCK
CONFIG_SYS_MATRIX_EBI0CSA_VAL
CONFIG_SYS_MATRIX_EBICSA_VAL
@@ -4907,6 +4915,7 @@ CONFIG_SYS_OR_TIMING_SDRAM
CONFIG_SYS_OSC0_HZ
CONFIG_SYS_OSC1_HZ
CONFIG_SYS_OSCIN_FREQ
+CONFIG_SYS_OSC_CLK
CONFIG_SYS_OSD_DH
CONFIG_SYS_OSD_SCREENS
CONFIG_SYS_OSPR_OFFSET
@@ -5244,6 +5253,7 @@ CONFIG_SYS_PIOC_PPUDR_VAL
CONFIG_SYS_PIOD_PDR_VAL1
CONFIG_SYS_PIOD_PPUDR_VAL
CONFIG_SYS_PIO_MODE
+CONFIG_SYS_PISCR
CONFIG_SYS_PIT_BASE
CONFIG_SYS_PIT_PRESCALE
CONFIG_SYS_PIXIS_VBOOT_ENABLE
@@ -5266,6 +5276,7 @@ CONFIG_SYS_PLL_FDR
CONFIG_SYS_PLL_ODR
CONFIG_SYS_PLL_RECONFIG
CONFIG_SYS_PLL_SETTLING_TIME
+CONFIG_SYS_PLPRCR
CONFIG_SYS_PLUG_BASE
CONFIG_SYS_PMAN
CONFIG_SYS_PMC_BASE
@@ -5579,6 +5590,7 @@ CONFIG_SYS_SICRH
CONFIG_SYS_SICRL
CONFIG_SYS_SIL1178_I2C
CONFIG_SYS_SIMULATE_SPD_EEPROM
+CONFIG_SYS_SIUMCR
CONFIG_SYS_SJA1000_BASE
CONFIG_SYS_SMALL_FLASH
CONFIG_SYS_SMC0_CYCLE0_VAL
@@ -5607,6 +5619,9 @@ CONFIG_SYS_SPI_ARGS_OFFS
CONFIG_SYS_SPI_ARGS_SIZE
CONFIG_SYS_SPI_BASE
CONFIG_SYS_SPI_CLK
+CONFIG_SYS_SPI_CS_ACT
+CONFIG_SYS_SPI_CS_BASE
+CONFIG_SYS_SPI_CS_USED
CONFIG_SYS_SPI_FLASH_U_BOOT_DST
CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS
CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE
@@ -5656,9 +5671,11 @@ CONFIG_SYS_STATUS_OK
CONFIG_SYS_STMICRO_BOOT
CONFIG_SYS_SUPPORT_64BIT_DATA
CONFIG_SYS_SXCNFG_VAL
+CONFIG_SYS_SYPCR
CONFIG_SYS_SYSTEMACE_BASE
CONFIG_SYS_SYSTEMACE_WIDTH
CONFIG_SYS_TBIPA_VALUE
+CONFIG_SYS_TBSCR
CONFIG_SYS_TCLK
CONFIG_SYS_TEMP_STACK_OCM
CONFIG_SYS_TEXT_ADDR
@@ -5754,6 +5771,7 @@ CONFIG_SYS_UECx_PHY_ADDR
CONFIG_SYS_UHC0_EHCI_BASE
CONFIG_SYS_UHC1_EHCI_BASE
CONFIG_SYS_ULB_CLK
+CONFIG_SYS_UMCR
CONFIG_SYS_UNIFY_CACHE
CONFIG_SYS_UNSPEC_PHYID
CONFIG_SYS_UNSPEC_STRID
--
2.12.0
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