[U-Boot] [PATCH 21/31] ARM: k2g: Program DDRPHY_DATX8 registers via mask and value variables
Franklin S Cooper Jr
fcooper at ti.com
Thu Mar 2 19:04:25 UTC 2017
Different K2G evms may need to program the various
KS2_DDRPHY_DATX8_X_OFFSET registers in different ways. Therefore, use
the mask and val registers for each KS2_DDRPHY_DATAX_X_OFFSET to
properly program the register.
Signed-off-by: Franklin S Cooper Jr <fcooper at ti.com>
---
arch/arm/mach-keystone/ddr3.c | 32 +++++++++++++++++++++++++++-----
board/ti/ks2_evm/ddr3_k2g.c | 14 ++++++++++++++
2 files changed, 41 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mach-keystone/ddr3.c b/arch/arm/mach-keystone/ddr3.c
index 25a9637..4cad6a2 100644
--- a/arch/arm/mach-keystone/ddr3.c
+++ b/arch/arm/mach-keystone/ddr3.c
@@ -65,11 +65,33 @@ void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg)
;
if (cpu_is_k2g()) {
- setbits_le32(base + KS2_DDRPHY_DATX8_4_OFFSET, 0x1);
- clrbits_le32(base + KS2_DDRPHY_DATX8_5_OFFSET, 0x1);
- clrbits_le32(base + KS2_DDRPHY_DATX8_6_OFFSET, 0x1);
- clrbits_le32(base + KS2_DDRPHY_DATX8_7_OFFSET, 0x1);
- clrbits_le32(base + KS2_DDRPHY_DATX8_8_OFFSET, 0x1);
+ clrsetbits_le32(base + KS2_DDRPHY_DATX8_2_OFFSET,
+ phy_cfg->datx8_2_mask,
+ phy_cfg->datx8_2_val);
+
+ clrsetbits_le32(base + KS2_DDRPHY_DATX8_3_OFFSET,
+ phy_cfg->datx8_3_mask,
+ phy_cfg->datx8_3_val);
+
+ clrsetbits_le32(base + KS2_DDRPHY_DATX8_4_OFFSET,
+ phy_cfg->datx8_4_mask,
+ phy_cfg->datx8_4_val);
+
+ clrsetbits_le32(base + KS2_DDRPHY_DATX8_5_OFFSET,
+ phy_cfg->datx8_5_mask,
+ phy_cfg->datx8_5_val);
+
+ clrsetbits_le32(base + KS2_DDRPHY_DATX8_6_OFFSET,
+ phy_cfg->datx8_6_mask,
+ phy_cfg->datx8_6_val);
+
+ clrsetbits_le32(base + KS2_DDRPHY_DATX8_7_OFFSET,
+ phy_cfg->datx8_7_mask,
+ phy_cfg->datx8_7_val);
+
+ clrsetbits_le32(base + KS2_DDRPHY_DATX8_8_OFFSET,
+ phy_cfg->datx8_8_mask,
+ phy_cfg->datx8_8_val);
}
__raw_writel(phy_cfg->pir_v2, base + KS2_DDRPHY_PIR_OFFSET);
diff --git a/board/ti/ks2_evm/ddr3_k2g.c b/board/ti/ks2_evm/ddr3_k2g.c
index aeb7da6..3b12943 100644
--- a/board/ti/ks2_evm/ddr3_k2g.c
+++ b/board/ti/ks2_evm/ddr3_k2g.c
@@ -34,6 +34,20 @@ struct ddr3_phy_config ddr3phy_800_2g = {
.zq1cr1 = 0x0001005Bul,
.zq2cr1 = 0x0001005Bul,
.pir_v1 = 0x00000033ul,
+ .datx8_2_mask = 0,
+ .datx8_2_val = 0,
+ .datx8_3_mask = 0,
+ .datx8_3_val = 0,
+ .datx8_4_mask = 0,
+ .datx8_4_val = ((1 << 0)),
+ .datx8_5_mask = DXEN_MASK,
+ .datx8_5_val = 0,
+ .datx8_6_mask = DXEN_MASK,
+ .datx8_6_val = 0,
+ .datx8_7_mask = DXEN_MASK,
+ .datx8_7_val = 0,
+ .datx8_8_mask = DXEN_MASK,
+ .datx8_8_val = 0,
.pir_v2 = 0x00000F81ul,
};
--
2.10.0
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