[U-Boot] [PATCH v2 2/8] Revert "spi: cadence_qspi_apb: Use 32 bit indirect read transaction when possible"

[Marek Vasut]

On 03/01/2017 05:36 PM, Rush, Jason A. wrote:
> This reverts commit b63b46313ed29e9b0c36b3d6b9407f6eade40c8f.
>
> The Cadence QSPI device does not work with caching (introduced with
> the bounce buffer in this commit) on the Altera SoC platform.
>
> Signed-off-by: Jason A. Rush <jason.rush at gd-ms.com>

Do we really need the reverts or can we just fix the commit(s) up somehow ?

> ---
> Changed in v2: None
>
>  drivers/spi/cadence_qspi_apb.c | 22 ++++++----------------
>  1 file changed, 6 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
> index a6787c3b47..df6a91fc9f 100644
> --- a/drivers/spi/cadence_qspi_apb.c
> +++ b/drivers/spi/cadence_qspi_apb.c
> @@ -633,8 +633,6 @@ int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat,
>  {
>  	unsigned int remaining = n_rx;
>  	unsigned int bytes_to_read = 0;
> -	struct bounce_buffer bb;
> -	u8 *bb_rxbuf;
>  	int ret;
>
>  	writel(n_rx, plat->regbase + CQSPI_REG_INDIRECTRDBYTES);
> @@ -643,11 +641,6 @@ int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat,
>  	writel(CQSPI_REG_INDIRECTRD_START,
>  	       plat->regbase + CQSPI_REG_INDIRECTRD);
>
> -	ret = bounce_buffer_start(&bb, (void *)rxbuf, n_rx, GEN_BB_WRITE);
> -	if (ret)
> -		return ret;
> -	bb_rxbuf = bb.bounce_buffer;
> -
>  	while (remaining > 0) {
>  		ret = cadence_qspi_wait_for_data(plat);
>  		if (ret < 0) {
> @@ -661,13 +654,12 @@ int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat,
>  			bytes_to_read *= CQSPI_FIFO_WIDTH;
>  			bytes_to_read = bytes_to_read > remaining ?
>  					remaining : bytes_to_read;
> -			readsl(plat->ahbbase, bb_rxbuf, bytes_to_read >> 2);
> -			if (bytes_to_read % 4)
> -				readsb(plat->ahbbase,
> -				       bb_rxbuf + rounddown(bytes_to_read, 4),
> -				       bytes_to_read % 4);
> -
> -			bb_rxbuf += bytes_to_read;
> +			/* Handle non-4-byte aligned access to avoid data abort. */
> +			if (((uintptr_t)rxbuf % 4) || (bytes_to_read % 4))
> +				readsb(plat->ahbbase, rxbuf, bytes_to_read);
> +			else
> +				readsl(plat->ahbbase, rxbuf, bytes_to_read >> 2);
> +			rxbuf += bytes_to_read;
>  			remaining -= bytes_to_read;
>  			bytes_to_read = cadence_qspi_get_rd_sram_level(plat);
>  		}
> @@ -684,7 +676,6 @@ int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat,
>  	/* Clear indirect completion status */
>  	writel(CQSPI_REG_INDIRECTRD_DONE,
>  	       plat->regbase + CQSPI_REG_INDIRECTRD);
> -	bounce_buffer_stop(&bb);
>
>  	return 0;
>
> @@ -692,7 +683,6 @@ failrd:
>  	/* Cancel the indirect read */
>  	writel(CQSPI_REG_INDIRECTRD_CANCEL,
>  	       plat->regbase + CQSPI_REG_INDIRECTRD);
> -	bounce_buffer_stop(&bb);
>  	return ret;
>  }
>
>