[U-Boot] [PATCH 3/4] arm: socfpga: Add Arria10 FPGA manager program assembly driver

[Chee Tien Fong]

From: Tien Fong Chee <tien.fong.chee at intel.com>

This patch adding the Arria10 FPGA manager program assembly driver
which can be used for feeding bitstream to configure FPGA.

Signed-off-by: Tien Fong Chee <tien.fong.chee at intel.com>
Cc: Marek Vasut <marex at denx.de>
Cc: Dinh Nguyen <dinguyen at kernel.org>
Cc: Ching Liang See <chin.liang.see at intel.com>
Cc: Ley Foon <ley.foon.tan at intel.com>
Cc: Westergreen Dalon <dalon.westergreen at intel.com>
---
 arch/arm/mach-socfpga/lowlevel_init.S |   48 +++++++++++++++++++++++++++++++++
 1 files changed, 48 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/lowlevel_init.S

diff --git a/arch/arm/mach-socfpga/lowlevel_init.S b/arch/arm/mach-socfpga/lowlevel_init.S
new file mode 100644
index 0000000..79e9d07
--- /dev/null
+++ b/arch/arm/mach-socfpga/lowlevel_init.S
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2017 Intel Corporation <www.intel.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <linux/linkage.h>
+
+/*
+ * Write RBF data in burst form to FPGA Manager
+ * [r0] RBF binary source address
+ * [r1] FPGA Manager data address
+ * [r2] RBF data length
+ */
+
+ENTRY(fpgamgr_axi_write)
+	PUSH    {r4-r11, lr}            /* save registers per AAPCS */
+
+write_burst:
+	cmp     r2,#32
+	beq     write_burst_cont
+	bls     write_word
+write_burst_cont:
+	ldmia   r0!, {r4-r11}
+	stmia   r1, {r4-r11}
+	subs    r2, r2, #32
+	b       write_burst
+
+write_word:
+	cmp     r2,#4
+	beq     write_word_cont
+	bls     write_byte
+write_word_cont:
+	ldmia   r0!, {r4}
+	stmia   r1, {r4}
+	subs    r2, r2, #4
+	b       write_word
+
+write_byte:
+	cmp     r2,#0
+	beq     write_end
+	ldr     r3, [r0]
+	str     r3, [r1]
+write_end:
+	POP     {r4-r11, pc}
+ENDPROC(fpgamgr_axi_write)
-- 
1.7.1