[U-Boot] [PATCH v2 2/8] Revert "spi: cadence_qspi_apb: Use 32 bit indirect read transaction when possible"

[Marek Vasut]

On 03/07/2017 04:18 PM, Rush, Jason A. wrote:
> Marek Vasut wrote:
>> On 03/03/2017 04:17 PM, Rush, Jason A. wrote:
>>> Marek Vasut wrote:
>>>> On 03/01/2017 05:36 PM, Rush, Jason A. wrote:
>>>>> This reverts commit b63b46313ed29e9b0c36b3d6b9407f6eade40c8f.
>>>>>
>>>>> The Cadence QSPI device does not work with caching (introduced with
>>>>> the bounce buffer in this commit) on the Altera SoC platform.
>>>>>
>>>>> Signed-off-by: Jason A. Rush <jason.rush at gd-ms.com>
>>>>
>>>> Do we really need the reverts or can we just fix the commit(s) up somehow ?
>>>>
>>>
>>> Would you prefer I squash the 2 reverts and the subsequent patch together
>>> as a single commit?
>>
>> I would prefer if you answered my question :) So let me re-iterate, can
>> we incrementally fix the driver instead of doing the revert(s) ?
> 
> I think I misunderstood your question.  Could you clarify what you mean by
> incrementally fix the driver?

That means change it to the final form without reverting patches.

> Are you asking if there is a way to fix the cache issue with the CQSPI on the
> Altera SoC platform?  If so, I don't know if I have the knowledge to answer that.
> Do you have any suggestions on where one would start looking to fix the
> caching problem?

Uh, there is a cache problem on socfpga ? Is this series working around
it then ?

> Just so we have a common understanding, the reverts along with the
> subsequent patches get the CQSPI device working again on the Altera SoC as
> it used to in previous versions of U-Boot, and the CQSPI should continue to
> work for the TI devices Vignesh's patches were intended to fix.
> 
> Regards,
> Jason
> 


-- 
Best regards,
Marek Vasut