[U-Boot] [PATCH 3/8] rockchip: video: Split out HDMI controller code
Nickey.Yang
nickey.yang at rock-chips.com
Fri Mar 10 02:19:44 UTC 2017
Hi Jernej,
在 2017年03月09日 07:34, Jernej Skrabec 写道:
> Designware HDMI controller and phy are used in other SoCs as well. Split
> out platform independent code.
>
> DW HDMI has 8 bit registers but they can be represented as 32 bit
> registers as well. Add support to select access mode.
>
> EDID reading code use reading by blocks which is not supported by other
> SoCs in general. Make it more general using byte by byte approach, which
> is also used in Linux driver.
>
> Finally, not all DW HDMI controllers are accompanied with DW HDMI phy.
> Support custom phys by making controller code independent from phy code.
>
> Signed-off-by: Jernej Skrabec <jernej.skrabec at siol.net>
> ---
I have tested this series of patches in rockchip rk3288 tinker boards.
Tested-by: Nickey Yang <nickey.yang at rock-chips.com>
> arch/arm/include/asm/arch-rockchip/hdmi_rk3288.h | 456 --------------
> drivers/video/dw_hdmi.c | 764 +++++++++++++++++++++++
> drivers/video/rockchip/Makefile | 2 +-
> drivers/video/rockchip/rk_hdmi.c | 757 +---------------------
> drivers/video/rockchip/rk_vop.c | 1 -
> include/dw_hdmi.h | 486 ++++++++++++++
> 6 files changed, 1275 insertions(+), 1191 deletions(-)
> delete mode 100644 arch/arm/include/asm/arch-rockchip/hdmi_rk3288.h
> create mode 100644 drivers/video/dw_hdmi.c
> create mode 100644 include/dw_hdmi.h
>
> diff --git a/arch/arm/include/asm/arch-rockchip/hdmi_rk3288.h b/arch/arm/include/asm/arch-rockchip/hdmi_rk3288.h
> deleted file mode 100644
> index 0b51d40882..0000000000
> --- a/arch/arm/include/asm/arch-rockchip/hdmi_rk3288.h
> +++ /dev/null
> @@ -1,456 +0,0 @@
> -/*
> - * Copyright (c) 2015 Google, Inc
> - * Copyright 2014 Rockchip Inc.
> - * Copyright (C) 2011 Freescale Semiconductor, Inc.
> - *
> - * SPDX-License-Identifier: GPL-2.0+
> - */
> -
> -#ifndef _ASM_ARCH_HDMI_H
> -#define _ASM_ARCH_HDMI_H
> -
> -
> -#define HDMI_EDID_BLOCK_SIZE 128
> -
> -struct rk3288_hdmi {
> - u32 reserved0[0x100];
> - u32 ih_fc_stat0;
> - u32 ih_fc_stat1;
> - u32 ih_fc_stat2;
> - u32 ih_as_stat0;
> - u32 ih_phy_stat0;
> - u32 ih_i2cm_stat0;
> - u32 ih_cec_stat0;
> - u32 ih_vp_stat0;
> - u32 ih_i2cmphy_stat0;
> - u32 ih_ahbdmaaud_stat0;
> - u32 reserved1[0x17f-0x109];
> - u32 ih_mute_fc_stat0;
> - u32 ih_mute_fc_stat1;
> - u32 ih_mute_fc_stat2;
> - u32 ih_mute_as_stat0;
> - u32 ih_mute_phy_stat0;
> - u32 ih_mute_i2cm_stat0;
> - u32 ih_mute_cec_stat0;
> - u32 ih_mute_vp_stat0;
> - u32 ih_mute_i2cmphy_stat0;
> - u32 ih_mute_ahbdmaaud_stat0;
> - u32 reserved2[0x1fe - 0x189];
> - u32 ih_mute;
> - u32 tx_invid0;
> - u32 tx_instuffing;
> - u32 tx_gydata0;
> - u32 tx_gydata1;
> - u32 tx_rcrdata0;
> - u32 tx_rcrdata1;
> - u32 tx_bcbdata0;
> - u32 tx_bcbdata1;
> - u32 reserved3[0x7ff-0x207];
> - u32 vp_status;
> - u32 vp_pr_cd;
> - u32 vp_stuff;
> - u32 vp_remap;
> - u32 vp_conf;
> - u32 vp_stat;
> - u32 vp_int;
> - u32 vp_mask;
> - u32 vp_pol;
> - u32 reserved4[0xfff-0x808];
> - u32 fc_invidconf;
> - u32 fc_inhactv0;
> - u32 fc_inhactv1;
> - u32 fc_inhblank0;
> - u32 fc_inhblank1;
> - u32 fc_invactv0;
> - u32 fc_invactv1;
> - u32 fc_invblank;
> - u32 fc_hsyncindelay0;
> - u32 fc_hsyncindelay1;
> - u32 fc_hsyncinwidth0;
> - u32 fc_hsyncinwidth1;
> - u32 fc_vsyncindelay;
> - u32 fc_vsyncinwidth;
> - u32 fc_infreq0;
> - u32 fc_infreq1;
> - u32 fc_infreq2;
> - u32 fc_ctrldur;
> - u32 fc_exctrldur;
> - u32 fc_exctrlspac;
> - u32 fc_ch0pream;
> - u32 fc_ch1pream;
> - u32 fc_ch2pream;
> - u32 fc_aviconf3;
> - u32 fc_gcp;
> - u32 fc_aviconf0;
> - u32 fc_aviconf1;
> - u32 fc_aviconf2;
> - u32 fc_avivid;
> - u32 fc_avietb0;
> - u32 fc_avietb1;
> - u32 fc_avisbb0;
> - u32 fc_avisbb1;
> - u32 fc_avielb0;
> - u32 fc_avielb1;
> - u32 fc_avisrb0;
> - u32 fc_avisrb1;
> - u32 fc_audiconf0;
> - u32 fc_audiconf1;
> - u32 fc_audiconf2;
> - u32 fc_audiconf3;
> - u32 fc_vsdieeeid0;
> - u32 fc_vsdsize;
> - u32 reserved7[0x2fff-0x102a];
> - u32 phy_conf0;
> - u32 phy_tst0;
> - u32 phy_tst1;
> - u32 phy_tst2;
> - u32 phy_stat0;
> - u32 phy_int0;
> - u32 phy_mask0;
> - u32 phy_pol0;
> - u32 reserved8[0x301f-0x3007];
> - u32 phy_i2cm_slave_addr;
> - u32 phy_i2cm_address_addr;
> - u32 phy_i2cm_datao_1_addr;
> - u32 phy_i2cm_datao_0_addr;
> - u32 phy_i2cm_datai_1_addr;
> - u32 phy_i2cm_datai_0_addr;
> - u32 phy_i2cm_operation_addr;
> - u32 phy_i2cm_int_addr;
> - u32 phy_i2cm_ctlint_addr;
> - u32 phy_i2cm_div_addr;
> - u32 phy_i2cm_softrstz_addr;
> - u32 phy_i2cm_ss_scl_hcnt_1_addr;
> - u32 phy_i2cm_ss_scl_hcnt_0_addr;
> - u32 phy_i2cm_ss_scl_lcnt_1_addr;
> - u32 phy_i2cm_ss_scl_lcnt_0_addr;
> - u32 phy_i2cm_fs_scl_hcnt_1_addr;
> - u32 phy_i2cm_fs_scl_hcnt_0_addr;
> - u32 phy_i2cm_fs_scl_lcnt_1_addr;
> - u32 phy_i2cm_fs_scl_lcnt_0_addr;
> - u32 reserved9[0x30ff-0x3032];
> - u32 aud_conf0;
> - u32 aud_conf1;
> - u32 aud_int;
> - u32 aud_conf2;
> - u32 aud_int1;
> - u32 reserved32[0x31ff-0x3104];
> - u32 aud_n1;
> - u32 aud_n2;
> - u32 aud_n3;
> - u32 aud_cts1;
> - u32 aud_cts2;
> - u32 aud_cts3;
> - u32 aud_inputclkfs;
> - u32 reserved12[0x3fff-0x3206];
> - u32 mc_sfrdiv;
> - u32 mc_clkdis;
> - u32 mc_swrstz;
> - u32 mc_opctrl;
> - u32 mc_flowctrl;
> - u32 mc_phyrstz;
> - u32 mc_lockonclock;
> - u32 mc_heacphy_rst;
> - u32 reserved13[0x40ff-0x4007];
> - u32 csc_cfg;
> - u32 csc_scale;
> - struct {
> - u32 msb;
> - u32 lsb;
> - } csc_coef[3][4];
> - u32 reserved17[0x7dff-0x4119];
> - u32 i2cm_slave;
> - u32 i2c_address;
> - u32 i2cm_datao;
> - u32 i2cm_datai;
> - u32 i2cm_operation;
> - u32 i2cm_int;
> - u32 i2cm_ctlint;
> - u32 i2cm_div;
> - u32 i2cm_segaddr;
> - u32 i2cm_softrstz;
> - u32 i2cm_segptr;
> - u32 i2cm_ss_scl_hcnt_1_addr;
> - u32 i2cm_ss_scl_hcnt_0_addr;
> - u32 i2cm_ss_scl_lcnt_1_addr;
> - u32 i2cm_ss_scl_lcnt_0_addr;
> - u32 i2cm_fs_scl_hcnt_1_addr;
> - u32 i2cm_fs_scl_hcnt_0_addr;
> - u32 i2cm_fs_scl_lcnt_1_addr;
> - u32 i2cm_fs_scl_lcnt_0_addr;
> - u32 reserved18[0x7e1f-0x7e12];
> - u32 i2cm_buf0;
> -};
> -check_member(rk3288_hdmi, i2cm_buf0, 0x1f880);
> -
> -enum {
> - /* HDMI PHY registers define */
> - PHY_OPMODE_PLLCFG = 0x06,
> - PHY_CKCALCTRL = 0x05,
> - PHY_CKSYMTXCTRL = 0x09,
> - PHY_VLEVCTRL = 0x0e,
> - PHY_PLLCURRCTRL = 0x10,
> - PHY_PLLPHBYCTRL = 0x13,
> - PHY_PLLGMPCTRL = 0x15,
> - PHY_PLLCLKBISTPHASE = 0x17,
> - PHY_TXTERM = 0x19,
> -
> - /* ih_phy_stat0 field values */
> - HDMI_IH_PHY_STAT0_HPD = 0x1,
> -
> - /* ih_mute field values */
> - HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT = 0x2,
> - HDMI_IH_MUTE_MUTE_ALL_INTERRUPT = 0x1,
> -
> - /* tx_invid0 field values */
> - HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE = 0x00,
> - HDMI_TX_INVID0_VIDEO_MAPPING_MASK = 0x1f,
> - HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET = 0,
> -
> - /* tx_instuffing field values */
> - HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE = 0x4,
> - HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE = 0x2,
> - HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE = 0x1,
> -
> - /* vp_pr_cd field values */
> - HDMI_VP_PR_CD_COLOR_DEPTH_MASK = 0xf0,
> - HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET = 4,
> - HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK = 0x0f,
> - HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET = 0,
> -
> - /* vp_stuff field values */
> - HDMI_VP_STUFF_IDEFAULT_PHASE_MASK = 0x20,
> - HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET = 5,
> - HDMI_VP_STUFF_YCC422_STUFFING_MASK = 0x4,
> - HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE = 0x4,
> - HDMI_VP_STUFF_PP_STUFFING_MASK = 0x2,
> - HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE = 0x2,
> - HDMI_VP_STUFF_PR_STUFFING_MASK = 0x1,
> - HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE = 0x1,
> -
> - /* vp_conf field values */
> - HDMI_VP_CONF_BYPASS_EN_MASK = 0x40,
> - HDMI_VP_CONF_BYPASS_EN_ENABLE = 0x40,
> - HDMI_VP_CONF_PP_EN_ENMASK = 0x20,
> - HDMI_VP_CONF_PP_EN_DISABLE = 0x00,
> - HDMI_VP_CONF_PR_EN_MASK = 0x10,
> - HDMI_VP_CONF_PR_EN_DISABLE = 0x00,
> - HDMI_VP_CONF_YCC422_EN_MASK = 0x8,
> - HDMI_VP_CONF_YCC422_EN_DISABLE = 0x0,
> - HDMI_VP_CONF_BYPASS_SELECT_MASK = 0x4,
> - HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER = 0x4,
> - HDMI_VP_CONF_OUTPUT_SELECTOR_MASK = 0x3,
> - HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS = 0x3,
> -
> - /* vp_remap field values */
> - HDMI_VP_REMAP_YCC422_16BIT = 0x0,
> -
> - /* fc_invidconf field values */
> - HDMI_FC_INVIDCONF_HDCP_KEEPOUT_MASK = 0x80,
> - HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE = 0x80,
> - HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE = 0x00,
> - HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_MASK = 0x40,
> - HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH = 0x40,
> - HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW = 0x00,
> - HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_MASK = 0x20,
> - HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH = 0x20,
> - HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW = 0x00,
> - HDMI_FC_INVIDCONF_DE_IN_POLARITY_MASK = 0x10,
> - HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH = 0x10,
> - HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW = 0x00,
> - HDMI_FC_INVIDCONF_DVI_MODEZ_MASK = 0x8,
> - HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE = 0x8,
> - HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE = 0x0,
> - HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_MASK = 0x2,
> - HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH = 0x2,
> - HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW = 0x0,
> - HDMI_FC_INVIDCONF_IN_I_P_MASK = 0x1,
> - HDMI_FC_INVIDCONF_IN_I_P_INTERLACED = 0x1,
> - HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE = 0x0,
> -
> -
> - /* fc_aviconf0-fc_aviconf3 field values */
> - HDMI_FC_AVICONF0_PIX_FMT_MASK = 0x03,
> - HDMI_FC_AVICONF0_PIX_FMT_RGB = 0x00,
> - HDMI_FC_AVICONF0_PIX_FMT_YCBCR422 = 0x01,
> - HDMI_FC_AVICONF0_PIX_FMT_YCBCR444 = 0x02,
> - HDMI_FC_AVICONF0_ACTIVE_FMT_MASK = 0x40,
> - HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT = 0x40,
> - HDMI_FC_AVICONF0_ACTIVE_FMT_NO_INFO = 0x00,
> - HDMI_FC_AVICONF0_BAR_DATA_MASK = 0x0c,
> - HDMI_FC_AVICONF0_BAR_DATA_NO_DATA = 0x00,
> - HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR = 0x04,
> - HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR = 0x08,
> - HDMI_FC_AVICONF0_BAR_DATA_VERT_HORIZ_BAR = 0x0c,
> - HDMI_FC_AVICONF0_SCAN_INFO_MASK = 0x30,
> - HDMI_FC_AVICONF0_SCAN_INFO_OVERSCAN = 0x10,
> - HDMI_FC_AVICONF0_SCAN_INFO_UNDERSCAN = 0x20,
> - HDMI_FC_AVICONF0_SCAN_INFO_NODATA = 0x00,
> -
> - HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_MASK = 0x0f,
> - HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_USE_CODED = 0x08,
> - HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_4_3 = 0x09,
> - HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_16_9 = 0x0a,
> - HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_14_9 = 0x0b,
> - HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_MASK = 0x30,
> - HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_NO_DATA = 0x00,
> - HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_4_3 = 0x10,
> - HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_16_9 = 0x20,
> - HDMI_FC_AVICONF1_COLORIMETRY_MASK = 0xc0,
> - HDMI_FC_AVICONF1_COLORIMETRY_NO_DATA = 0x00,
> - HDMI_FC_AVICONF1_COLORIMETRY_SMPTE = 0x40,
> - HDMI_FC_AVICONF1_COLORIMETRY_ITUR = 0x80,
> - HDMI_FC_AVICONF1_COLORIMETRY_EXTENDED_INFO = 0xc0,
> -
> - HDMI_FC_AVICONF2_SCALING_MASK = 0x03,
> - HDMI_FC_AVICONF2_SCALING_NONE = 0x00,
> - HDMI_FC_AVICONF2_SCALING_HORIZ = 0x01,
> - HDMI_FC_AVICONF2_SCALING_VERT = 0x02,
> - HDMI_FC_AVICONF2_SCALING_HORIZ_vert = 0x03,
> - HDMI_FC_AVICONF2_RGB_QUANT_MASK = 0x0c,
> - HDMI_FC_AVICONF2_RGB_QUANT_DEFAULT = 0x00,
> - HDMI_FC_AVICONF2_RGB_QUANT_LIMITED_RANGE = 0x04,
> - HDMI_FC_AVICONF2_RGB_QUANT_FULL_RANGE = 0x08,
> - HDMI_FC_AVICONF2_EXT_COLORIMETRY_MASK = 0x70,
> - HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601 = 0x00,
> - HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC709 = 0x10,
> - HDMI_FC_AVICONF2_EXT_COLORIMETRY_SYCC601 = 0x20,
> - HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_YCC601 = 0x30,
> - HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_RGB = 0x40,
> - HDMI_FC_AVICONF2_IT_CONTENT_MASK = 0x80,
> - HDMI_FC_AVICONF2_IT_CONTENT_NO_DATA = 0x00,
> - HDMI_FC_AVICONF2_IT_CONTENT_VALID = 0x80,
> -
> - HDMI_FC_AVICONF3_IT_CONTENT_TYPE_MASK = 0x03,
> - HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GRAPHICS = 0x00,
> - HDMI_FC_AVICONF3_IT_CONTENT_TYPE_PHOTO = 0x01,
> - HDMI_FC_AVICONF3_IT_CONTENT_TYPE_CINEMA = 0x02,
> - HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GAME = 0x03,
> - HDMI_FC_AVICONF3_QUANT_RANGE_MASK = 0x0c,
> - HDMI_FC_AVICONF3_QUANT_RANGE_LIMITED = 0x00,
> - HDMI_FC_AVICONF3_QUANT_RANGE_FULL = 0x04,
> -
> - /* fc_gcp field values*/
> - HDMI_FC_GCP_SET_AVMUTE = 0x02,
> - HDMI_FC_GCP_CLEAR_AVMUTE = 0x01,
> -
> - /* phy_conf0 field values */
> - HDMI_PHY_CONF0_PDZ_MASK = 0x80,
> - HDMI_PHY_CONF0_PDZ_OFFSET = 7,
> - HDMI_PHY_CONF0_ENTMDS_MASK = 0x40,
> - HDMI_PHY_CONF0_ENTMDS_OFFSET = 6,
> - HDMI_PHY_CONF0_SPARECTRL_MASK = 0x20,
> - HDMI_PHY_CONF0_SPARECTRL_OFFSET = 5,
> - HDMI_PHY_CONF0_GEN2_PDDQ_MASK = 0x10,
> - HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET = 4,
> - HDMI_PHY_CONF0_GEN2_TXPWRON_MASK = 0x8,
> - HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET = 3,
> - HDMI_PHY_CONF0_SELDATAENPOL_MASK = 0x2,
> - HDMI_PHY_CONF0_SELDATAENPOL_OFFSET = 1,
> - HDMI_PHY_CONF0_SELDIPIF_MASK = 0x1,
> - HDMI_PHY_CONF0_SELDIPIF_OFFSET = 0,
> -
> - /* phy_tst0 field values */
> - HDMI_PHY_TST0_TSTCLR_MASK = 0x20,
> - HDMI_PHY_TST0_TSTCLR_OFFSET = 5,
> -
> - /* phy_stat0 field values */
> - HDMI_PHY_HPD = 0x02,
> - HDMI_PHY_TX_PHY_LOCK = 0x01,
> -
> - /* phy_i2cm_slave_addr field values */
> - HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2 = 0x69,
> -
> - /* phy_i2cm_operation_addr field values */
> - HDMI_PHY_I2CM_OPERATION_ADDR_WRITE = 0x10,
> -
> - /* hdmi_phy_i2cm_int_addr */
> - HDMI_PHY_I2CM_INT_ADDR_DONE_POL = 0x08,
> -
> - /* hdmi_phy_i2cm_ctlint_addr */
> - HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL = 0x80,
> - HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL = 0x08,
> -
> - /* aud_conf0 field values */
> - HDMI_AUD_CONF0_SW_AUDIO_FIFO_RST = 0x80,
> - HDMI_AUD_CONF0_I2S_SELECT = 0x20,
> - HDMI_AUD_CONF0_I2S_IN_EN_0 = 0x01,
> - HDMI_AUD_CONF0_I2S_IN_EN_1 = 0x02,
> - HDMI_AUD_CONF0_I2S_IN_EN_2 = 0x04,
> - HDMI_AUD_CONF0_I2S_IN_EN_3 = 0x08,
> -
> - /* aud_conf0 field values */
> - HDMI_AUD_CONF1_I2S_MODE_STANDARD_MODE = 0x0,
> - HDMI_AUD_CONF1_I2S_WIDTH_16BIT = 0x10,
> -
> - /* aud_n3 field values */
> - HDMI_AUD_N3_NCTS_ATOMIC_WRITE = 0x80,
> - HDMI_AUD_N3_AUDN19_16_MASK = 0x0f,
> -
> - /* aud_cts3 field values */
> - HDMI_AUD_CTS3_N_SHIFT_OFFSET = 5,
> - HDMI_AUD_CTS3_N_SHIFT_MASK = 0xe0,
> - HDMI_AUD_CTS3_N_SHIFT_1 = 0,
> - HDMI_AUD_CTS3_N_SHIFT_16 = 0x20,
> - HDMI_AUD_CTS3_N_SHIFT_32 = 0x40,
> - HDMI_AUD_CTS3_N_SHIFT_64 = 0x60,
> - HDMI_AUD_CTS3_N_SHIFT_128 = 0x80,
> - HDMI_AUD_CTS3_N_SHIFT_256 = 0xa0,
> - HDMI_AUD_CTS3_CTS_MANUAL = 0x10,
> - HDMI_AUD_CTS3_AUDCTS19_16_MASK = 0x0f,
> -
> - /* aud_inputclkfs filed values */
> - HDMI_AUD_INPUTCLKFS_128 = 0x0,
> -
> - /* mc_clkdis field values */
> - HDMI_MC_CLKDIS_AUDCLK_DISABLE = 0x8,
> - HDMI_MC_CLKDIS_TMDSCLK_DISABLE = 0x2,
> - HDMI_MC_CLKDIS_PIXELCLK_DISABLE = 0x1,
> -
> - /* mc_swrstz field values */
> - HDMI_MC_SWRSTZ_II2SSWRST_REQ = 0x08,
> - HDMI_MC_SWRSTZ_TMDSSWRST_REQ = 0x02,
> -
> - /* mc_flowctrl field values */
> - HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH = 0x1,
> - HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS = 0x0,
> -
> - /* mc_phyrstz field values */
> - HDMI_MC_PHYRSTZ_ASSERT = 0x0,
> - HDMI_MC_PHYRSTZ_DEASSERT = 0x1,
> -
> - /* mc_heacphy_rst field values */
> - HDMI_MC_HEACPHY_RST_ASSERT = 0x1,
> -
> - /* csc_cfg field values */
> - HDMI_CSC_CFG_INTMODE_DISABLE = 0x00,
> -
> - /* csc_scale field values */
> - HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK = 0xf0,
> - HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP = 0x00,
> - HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP = 0x50,
> - HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP = 0x60,
> - HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP = 0x70,
> - HDMI_CSC_SCALE_CSCSCALE_MASK = 0x03,
> -
> - /* i2cm filed values */
> - HDMI_I2CM_SLAVE_DDC_ADDR = 0x50,
> - HDMI_I2CM_SEGADDR_DDC = 0x30,
> - HDMI_I2CM_OPT_RD8_EXT = 0x8,
> - HDMI_I2CM_OPT_RD8 = 0x4,
> - HDMI_I2CM_DIV_FAST_STD_MODE = 0x8,
> - HDMI_I2CM_DIV_FAST_MODE = 0x8,
> - HDMI_I2CM_DIV_STD_MODE = 0x0,
> - HDMI_I2CM_SOFTRSTZ = 0x1,
> -};
> -
> -/*
> -struct display_timing;
> -struct rk3288_grf;
> -
> -int rk_hdmi_init(struct rk3288_grf *grf, u32 vop_id);
> -int rk_hdmi_enable(const struct display_timing *edid);
> -int rk_hdmi_get_edid(struct rk3288_grf *grf, struct display_timing *edid);
> -*/
> -
> -#endif
> diff --git a/drivers/video/dw_hdmi.c b/drivers/video/dw_hdmi.c
> new file mode 100644
> index 0000000000..8a53109823
> --- /dev/null
> +++ b/drivers/video/dw_hdmi.c
> @@ -0,0 +1,764 @@
> +/*
> + * Copyright (c) 2015 Google, Inc
> + * Copyright 2014 Rockchip Inc.
> + * Copyright 2017 Jernej Skrabec <jernej.skrabec at siol.net>
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <fdtdec.h>
> +#include <asm/io.h>
> +#include "dw_hdmi.h"
> +
> +struct tmds_n_cts {
> + u32 tmds;
> + u32 cts;
> + u32 n;
> +};
> +
> +static const struct tmds_n_cts n_cts_table[] = {
> + {
> + .tmds = 25175000, .n = 6144, .cts = 25175,
> + }, {
> + .tmds = 25200000, .n = 6144, .cts = 25200,
> + }, {
> + .tmds = 27000000, .n = 6144, .cts = 27000,
> + }, {
> + .tmds = 27027000, .n = 6144, .cts = 27027,
> + }, {
> + .tmds = 40000000, .n = 6144, .cts = 40000,
> + }, {
> + .tmds = 54000000, .n = 6144, .cts = 54000,
> + }, {
> + .tmds = 54054000, .n = 6144, .cts = 54054,
> + }, {
> + .tmds = 65000000, .n = 6144, .cts = 65000,
> + }, {
> + .tmds = 74176000, .n = 11648, .cts = 140625,
> + }, {
> + .tmds = 74250000, .n = 6144, .cts = 74250,
> + }, {
> + .tmds = 83500000, .n = 6144, .cts = 83500,
> + }, {
> + .tmds = 106500000, .n = 6144, .cts = 106500,
> + }, {
> + .tmds = 108000000, .n = 6144, .cts = 108000,
> + }, {
> + .tmds = 148352000, .n = 5824, .cts = 140625,
> + }, {
> + .tmds = 148500000, .n = 6144, .cts = 148500,
> + }, {
> + .tmds = 297000000, .n = 5120, .cts = 247500,
> + }
> +};
> +
> +static void hdmi_write(struct dw_hdmi *hdmi, u8 val, int offset)
> +{
> + switch (hdmi->reg_io_width) {
> + case 1:
> + writeb(val, hdmi->ioaddr + offset);
> + break;
> + case 4:
> + writel(val, hdmi->ioaddr + (offset << 2));
> + break;
> + default:
> + debug("reg_io_width has unsupported width!\n");
> + break;
> + }
> +}
> +
> +static u8 hdmi_read(struct dw_hdmi *hdmi, int offset)
> +{
> + switch (hdmi->reg_io_width) {
> + case 1:
> + return readb(hdmi->ioaddr + offset);
> + case 4:
> + return readl(hdmi->ioaddr + (offset << 2));
> + default:
> + debug("reg_io_width has unsupported width!\n");
> + break;
> + }
> +
> + return 0;
> +}
> +
> +static void hdmi_mod(struct dw_hdmi *hdmi, unsigned reg, u8 mask, u8 data)
> +{
> + u8 val = hdmi_read(hdmi, reg) & ~mask;
> +
> + val |= data & mask;
> + hdmi_write(hdmi, val, reg);
> +}
> +
> +static void hdmi_set_clock_regenerator(struct dw_hdmi *hdmi, u32 n, u32 cts)
> +{
> + uint cts3;
> + uint n3;
> +
> + /* first set ncts_atomic_write (if present) */
> + n3 = HDMI_AUD_N3_NCTS_ATOMIC_WRITE;
> + hdmi_write(hdmi, n3, HDMI_AUD_N3);
> +
> + /* set cts_manual (if present) */
> + cts3 = HDMI_AUD_CTS3_CTS_MANUAL;
> +
> + cts3 |= HDMI_AUD_CTS3_N_SHIFT_1 << HDMI_AUD_CTS3_N_SHIFT_OFFSET;
> + cts3 |= (cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK;
> +
> + /* write cts values; cts3 must be written first */
> + hdmi_write(hdmi, cts3, HDMI_AUD_CTS3);
> + hdmi_write(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2);
> + hdmi_write(hdmi, cts & 0xff, HDMI_AUD_CTS1);
> +
> + /* write n values; n1 must be written last */
> + n3 |= (n >> 16) & HDMI_AUD_N3_AUDN19_16_MASK;
> + hdmi_write(hdmi, n3, HDMI_AUD_N3);
> + hdmi_write(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2);
> + hdmi_write(hdmi, n & 0xff, HDMI_AUD_N3);
> +
> + hdmi_write(hdmi, HDMI_AUD_INPUTCLKFS_128, HDMI_AUD_INPUTCLKFS);
> +}
> +
> +static int hdmi_lookup_n_cts(u32 pixel_clk)
> +{
> + int i;
> +
> + for (i = 0; i < ARRAY_SIZE(n_cts_table); i++)
> + if (pixel_clk <= n_cts_table[i].tmds)
> + break;
> +
> + if (i >= ARRAY_SIZE(n_cts_table))
> + return -1;
> +
> + return i;
> +}
> +
> +static void hdmi_audio_set_samplerate(struct dw_hdmi *hdmi, u32 pixel_clk)
> +{
> + u32 clk_n, clk_cts;
> + int index;
> +
> + index = hdmi_lookup_n_cts(pixel_clk);
> + if (index == -1) {
> + debug("audio not supported for pixel clk %d\n", pixel_clk);
> + return;
> + }
> +
> + clk_n = n_cts_table[index].n;
> + clk_cts = n_cts_table[index].cts;
> + hdmi_set_clock_regenerator(hdmi, clk_n, clk_cts);
> +}
> +
> +/*
> + * this submodule is responsible for the video data synchronization.
> + * for example, for rgb 4:4:4 input, the data map is defined as
> + * pin{47~40} <==> r[7:0]
> + * pin{31~24} <==> g[7:0]
> + * pin{15~8} <==> b[7:0]
> + */
> +static void hdmi_video_sample(struct dw_hdmi *hdmi)
> +{
> + u32 color_format = 0x01;
> + uint val;
> +
> + val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE |
> + ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) &
> + HDMI_TX_INVID0_VIDEO_MAPPING_MASK);
> +
> + hdmi_write(hdmi, val, HDMI_TX_INVID0);
> +
> + /* enable tx stuffing: when de is inactive, fix the output data to 0 */
> + val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE |
> + HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE |
> + HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE;
> + hdmi_write(hdmi, val, HDMI_TX_INSTUFFING);
> + hdmi_write(hdmi, 0x0, HDMI_TX_GYDATA0);
> + hdmi_write(hdmi, 0x0, HDMI_TX_GYDATA1);
> + hdmi_write(hdmi, 0x0, HDMI_TX_RCRDATA0);
> + hdmi_write(hdmi, 0x0, HDMI_TX_RCRDATA1);
> + hdmi_write(hdmi, 0x0, HDMI_TX_BCBDATA0);
> + hdmi_write(hdmi, 0x0, HDMI_TX_BCBDATA1);
> +}
> +
> +static void hdmi_video_packetize(struct dw_hdmi *hdmi)
> +{
> + u32 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
> + u32 remap_size = HDMI_VP_REMAP_YCC422_16BIT;
> + u32 color_depth = 0;
> + uint val, vp_conf;
> +
> + /* set the packetizer registers */
> + val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) &
> + HDMI_VP_PR_CD_COLOR_DEPTH_MASK) |
> + ((0 << HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) &
> + HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK);
> + hdmi_write(hdmi, val, HDMI_VP_PR_CD);
> +
> + hdmi_mod(hdmi, HDMI_VP_STUFF, HDMI_VP_STUFF_PR_STUFFING_MASK,
> + HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE);
> +
> + /* data from pixel repeater block */
> + vp_conf = HDMI_VP_CONF_PR_EN_DISABLE |
> + HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER;
> +
> + hdmi_mod(hdmi, HDMI_VP_CONF, HDMI_VP_CONF_PR_EN_MASK |
> + HDMI_VP_CONF_BYPASS_SELECT_MASK, vp_conf);
> +
> + hdmi_mod(hdmi, HDMI_VP_STUFF, HDMI_VP_STUFF_IDEFAULT_PHASE_MASK,
> + 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET);
> +
> + hdmi_write(hdmi, remap_size, HDMI_VP_REMAP);
> +
> + vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE |
> + HDMI_VP_CONF_PP_EN_DISABLE |
> + HDMI_VP_CONF_YCC422_EN_DISABLE;
> +
> + hdmi_mod(hdmi, HDMI_VP_CONF, HDMI_VP_CONF_BYPASS_EN_MASK |
> + HDMI_VP_CONF_PP_EN_ENMASK | HDMI_VP_CONF_YCC422_EN_MASK,
> + vp_conf);
> +
> + hdmi_mod(hdmi, HDMI_VP_STUFF, HDMI_VP_STUFF_PP_STUFFING_MASK |
> + HDMI_VP_STUFF_YCC422_STUFFING_MASK,
> + HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE |
> + HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE);
> +
> + hdmi_mod(hdmi, HDMI_VP_CONF, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK,
> + output_select);
> +}
> +
> +static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi, uint bit)
> +{
> + hdmi_mod(hdmi, HDMI_PHY_TST0, HDMI_PHY_TST0_TSTCLR_MASK,
> + bit << HDMI_PHY_TST0_TSTCLR_OFFSET);
> +}
> +
> +static int hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, u32 msec)
> +{
> + ulong start;
> + u32 val;
> +
> + start = get_timer(0);
> + do {
> + val = hdmi_read(hdmi, HDMI_IH_I2CMPHY_STAT0);
> + if (val & 0x3) {
> + hdmi_write(hdmi, val, HDMI_IH_I2CMPHY_STAT0);
> + return 0;
> + }
> +
> + udelay(100);
> + } while (get_timer(start) < msec);
> +
> + return 1;
> +}
> +
> +static void hdmi_phy_i2c_write(struct dw_hdmi *hdmi, uint data, uint addr)
> +{
> + hdmi_write(hdmi, 0xff, HDMI_IH_I2CMPHY_STAT0);
> + hdmi_write(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR);
> + hdmi_write(hdmi, (u8)(data >> 8), HDMI_PHY_I2CM_DATAO_1_ADDR);
> + hdmi_write(hdmi, (u8)(data >> 0), HDMI_PHY_I2CM_DATAO_0_ADDR);
> + hdmi_write(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE,
> + HDMI_PHY_I2CM_OPERATION_ADDR);
> +
> + hdmi_phy_wait_i2c_done(hdmi, 1000);
> +}
> +
> +static void hdmi_phy_enable_power(struct dw_hdmi *hdmi, uint enable)
> +{
> + hdmi_mod(hdmi, HDMI_PHY_CONF0, HDMI_PHY_CONF0_PDZ_MASK,
> + enable << HDMI_PHY_CONF0_PDZ_OFFSET);
> +}
> +
> +static void hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, uint enable)
> +{
> + hdmi_mod(hdmi, HDMI_PHY_CONF0, HDMI_PHY_CONF0_ENTMDS_MASK,
> + enable << HDMI_PHY_CONF0_ENTMDS_OFFSET);
> +}
> +
> +static void hdmi_phy_enable_spare(struct dw_hdmi *hdmi, uint enable)
> +{
> + hdmi_mod(hdmi, HDMI_PHY_CONF0, HDMI_PHY_CONF0_SPARECTRL_MASK,
> + enable << HDMI_PHY_CONF0_SPARECTRL_OFFSET);
> +}
> +
> +static void hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, uint enable)
> +{
> + hdmi_mod(hdmi, HDMI_PHY_CONF0, HDMI_PHY_CONF0_GEN2_PDDQ_MASK,
> + enable << HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET);
> +}
> +
> +static void hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, uint enable)
> +{
> + hdmi_mod(hdmi, HDMI_PHY_CONF0,
> + HDMI_PHY_CONF0_GEN2_TXPWRON_MASK,
> + enable << HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET);
> +}
> +
> +static void hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, uint enable)
> +{
> + hdmi_mod(hdmi, HDMI_PHY_CONF0,
> + HDMI_PHY_CONF0_SELDATAENPOL_MASK,
> + enable << HDMI_PHY_CONF0_SELDATAENPOL_OFFSET);
> +}
> +
> +static void hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi,
> + uint enable)
> +{
> + hdmi_mod(hdmi, HDMI_PHY_CONF0, HDMI_PHY_CONF0_SELDIPIF_MASK,
> + enable << HDMI_PHY_CONF0_SELDIPIF_OFFSET);
> +}
> +
> +static int hdmi_phy_configure(struct dw_hdmi *hdmi, u32 mpixelclock)
> +{
> + ulong start;
> + uint i, val;
> +
> + if (!hdmi->mpll_cfg || !hdmi->phy_cfg)
> + return -1;
> +
> + /* gen2 tx power off */
> + hdmi_phy_gen2_txpwron(hdmi, 0);
> +
> + /* gen2 pddq */
> + hdmi_phy_gen2_pddq(hdmi, 1);
> +
> + /* phy reset */
> + hdmi_write(hdmi, HDMI_MC_PHYRSTZ_DEASSERT, HDMI_MC_PHYRSTZ);
> + hdmi_write(hdmi, HDMI_MC_PHYRSTZ_ASSERT, HDMI_MC_PHYRSTZ);
> + hdmi_write(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST);
> +
> + hdmi_phy_test_clear(hdmi, 1);
> + hdmi_write(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2,
> + HDMI_PHY_I2CM_SLAVE_ADDR);
> + hdmi_phy_test_clear(hdmi, 0);
> +
> + /* pll/mpll cfg - always match on final entry */
> + for (i = 0; hdmi->mpll_cfg[i].mpixelclock != (~0ul); i++)
> + if (mpixelclock <= hdmi->mpll_cfg[i].mpixelclock)
> + break;
> +
> + hdmi_phy_i2c_write(hdmi, hdmi->mpll_cfg[i].cpce, PHY_OPMODE_PLLCFG);
> + hdmi_phy_i2c_write(hdmi, hdmi->mpll_cfg[i].gmp, PHY_PLLGMPCTRL);
> + hdmi_phy_i2c_write(hdmi, hdmi->mpll_cfg[i].curr, PHY_PLLCURRCTRL);
> +
> + hdmi_phy_i2c_write(hdmi, 0x0000, PHY_PLLPHBYCTRL);
> + hdmi_phy_i2c_write(hdmi, 0x0006, PHY_PLLCLKBISTPHASE);
> +
> + for (i = 0; hdmi->phy_cfg[i].mpixelclock != (~0ul); i++)
> + if (mpixelclock <= hdmi->phy_cfg[i].mpixelclock)
> + break;
> +
> + /*
> + * resistance term 133ohm cfg
> + * preemp cgf 0.00
> + * tx/ck lvl 10
> + */
> + hdmi_phy_i2c_write(hdmi, hdmi->phy_cfg[i].term, PHY_TXTERM);
> + hdmi_phy_i2c_write(hdmi, hdmi->phy_cfg[i].sym_ctr, PHY_CKSYMTXCTRL);
> + hdmi_phy_i2c_write(hdmi, hdmi->phy_cfg[i].vlev_ctr, PHY_VLEVCTRL);
> +
> + /* remove clk term */
> + hdmi_phy_i2c_write(hdmi, 0x8000, PHY_CKCALCTRL);
> +
> + hdmi_phy_enable_power(hdmi, 1);
> +
> + /* toggle tmds enable */
> + hdmi_phy_enable_tmds(hdmi, 0);
> + hdmi_phy_enable_tmds(hdmi, 1);
> +
> + /* gen2 tx power on */
> + hdmi_phy_gen2_txpwron(hdmi, 1);
> + hdmi_phy_gen2_pddq(hdmi, 0);
> +
> + hdmi_phy_enable_spare(hdmi, 1);
> +
> + /* wait for phy pll lock */
> + start = get_timer(0);
> + do {
> + val = hdmi_read(hdmi, HDMI_PHY_STAT0);
> + if (!(val & HDMI_PHY_TX_PHY_LOCK))
> + return 0;
> +
> + udelay(100);
> + } while (get_timer(start) < 5);
> +
> + return -1;
> +}
> +
> +static void hdmi_av_composer(struct dw_hdmi *hdmi,
> + const struct display_timing *edid)
> +{
> + bool mdataenablepolarity = true;
> + uint inv_val;
> + uint hbl;
> + uint vbl;
> +
> + hbl = edid->hback_porch.typ + edid->hfront_porch.typ +
> + edid->hsync_len.typ;
> + vbl = edid->vback_porch.typ + edid->vfront_porch.typ +
> + edid->vsync_len.typ;
> +
> + /* set up hdmi_fc_invidconf */
> + inv_val = HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE;
> +
> + inv_val |= (edid->flags & DISPLAY_FLAGS_HSYNC_HIGH ?
> + HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH :
> + HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW);
> +
> + inv_val |= (edid->flags & DISPLAY_FLAGS_VSYNC_HIGH ?
> + HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH :
> + HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW);
> +
> + inv_val |= (mdataenablepolarity ?
> + HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH :
> + HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW);
> +
> + /*
> + * TODO(sjg at chromium.org>: Need to check for HDMI / DVI
> + * inv_val |= (edid->hdmi_monitor_detected ?
> + * HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE :
> + * HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE);
> + */
> + inv_val |= HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE;
> +
> + inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW;
> +
> + inv_val |= HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE;
> +
> + hdmi_write(hdmi, inv_val, HDMI_FC_INVIDCONF);
> +
> + /* set up horizontal active pixel width */
> + hdmi_write(hdmi, edid->hactive.typ >> 8, HDMI_FC_INHACTV1);
> + hdmi_write(hdmi, edid->hactive.typ, HDMI_FC_INHACTV0);
> +
> + /* set up vertical active lines */
> + hdmi_write(hdmi, edid->vactive.typ >> 8, HDMI_FC_INVACTV1);
> + hdmi_write(hdmi, edid->vactive.typ, HDMI_FC_INVACTV0);
> +
> + /* set up horizontal blanking pixel region width */
> + hdmi_write(hdmi, hbl >> 8, HDMI_FC_INHBLANK1);
> + hdmi_write(hdmi, hbl, HDMI_FC_INHBLANK0);
> +
> + /* set up vertical blanking pixel region width */
> + hdmi_write(hdmi, vbl, HDMI_FC_INVBLANK);
> +
> + /* set up hsync active edge delay width (in pixel clks) */
> + hdmi_write(hdmi, edid->hfront_porch.typ >> 8, HDMI_FC_HSYNCINDELAY1);
> + hdmi_write(hdmi, edid->hfront_porch.typ, HDMI_FC_HSYNCINDELAY0);
> +
> + /* set up vsync active edge delay (in lines) */
> + hdmi_write(hdmi, edid->vfront_porch.typ, HDMI_FC_VSYNCINDELAY);
> +
> + /* set up hsync active pulse width (in pixel clks) */
> + hdmi_write(hdmi, edid->hsync_len.typ >> 8, HDMI_FC_HSYNCINWIDTH1);
> + hdmi_write(hdmi, edid->hsync_len.typ, HDMI_FC_HSYNCINWIDTH0);
> +
> + /* set up vsync active edge delay (in lines) */
> + hdmi_write(hdmi, edid->vsync_len.typ, HDMI_FC_VSYNCINWIDTH);
> +}
> +
> +/* hdmi initialization step b.4 */
> +static void hdmi_enable_video_path(struct dw_hdmi *hdmi)
> +{
> + uint clkdis;
> +
> + /* control period minimum duration */
> + hdmi_write(hdmi, 12, HDMI_FC_CTRLDUR);
> + hdmi_write(hdmi, 32, HDMI_FC_EXCTRLDUR);
> + hdmi_write(hdmi, 1, HDMI_FC_EXCTRLSPAC);
> +
> + /* set to fill tmds data channels */
> + hdmi_write(hdmi, 0x0b, HDMI_FC_CH0PREAM);
> + hdmi_write(hdmi, 0x16, HDMI_FC_CH1PREAM);
> + hdmi_write(hdmi, 0x21, HDMI_FC_CH2PREAM);
> +
> + hdmi_write(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS,
> + HDMI_MC_FLOWCTRL);
> +
> + /* enable pixel clock and tmds data path */
> + clkdis = 0x7f;
> + clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE;
> + hdmi_write(hdmi, clkdis, HDMI_MC_CLKDIS);
> +
> + clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
> + hdmi_write(hdmi, clkdis, HDMI_MC_CLKDIS);
> +
> + clkdis &= ~HDMI_MC_CLKDIS_AUDCLK_DISABLE;
> + hdmi_write(hdmi, clkdis, HDMI_MC_CLKDIS);
> +}
> +
> +/* workaround to clear the overflow condition */
> +static void hdmi_clear_overflow(struct dw_hdmi *hdmi)
> +{
> + uint val, count;
> +
> + /* tmds software reset */
> + hdmi_write(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ);
> +
> + val = hdmi_read(hdmi, HDMI_FC_INVIDCONF);
> +
> + for (count = 0; count < 4; count++)
> + hdmi_write(hdmi, val, HDMI_FC_INVIDCONF);
> +}
> +
> +static void hdmi_audio_set_format(struct dw_hdmi *hdmi)
> +{
> + hdmi_write(hdmi, HDMI_AUD_CONF0_I2S_SELECT | HDMI_AUD_CONF0_I2S_IN_EN_0,
> + HDMI_AUD_CONF0);
> +
> +
> + hdmi_write(hdmi, HDMI_AUD_CONF1_I2S_MODE_STANDARD_MODE |
> + HDMI_AUD_CONF1_I2S_WIDTH_16BIT, HDMI_AUD_CONF1);
> +
> + hdmi_write(hdmi, 0x00, HDMI_AUD_CONF2);
> +}
> +
> +static void hdmi_audio_fifo_reset(struct dw_hdmi *hdmi)
> +{
> + hdmi_write(hdmi, (u8)~HDMI_MC_SWRSTZ_II2SSWRST_REQ, HDMI_MC_SWRSTZ);
> + hdmi_write(hdmi, HDMI_AUD_CONF0_SW_AUDIO_FIFO_RST, HDMI_AUD_CONF0);
> +
> + hdmi_write(hdmi, 0x00, HDMI_AUD_INT);
> + hdmi_write(hdmi, 0x00, HDMI_AUD_INT1);
> +}
> +
> +static int hdmi_get_plug_in_status(struct dw_hdmi *hdmi)
> +{
> + uint val = hdmi_read(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD;
> +
> + return !!val;
> +}
> +
> +static int hdmi_ddc_wait_i2c_done(struct dw_hdmi *hdmi, int msec)
> +{
> + u32 val;
> + ulong start;
> +
> + start = get_timer(0);
> + do {
> + val = hdmi_read(hdmi, HDMI_IH_I2CM_STAT0);
> + if (val & 0x2) {
> + hdmi_write(hdmi, val, HDMI_IH_I2CM_STAT0);
> + return 0;
> + }
> +
> + udelay(100);
> + } while (get_timer(start) < msec);
> +
> + return 1;
> +}
> +
> +static void hdmi_ddc_reset(struct dw_hdmi *hdmi)
> +{
> + hdmi_mod(hdmi, HDMI_I2CM_SOFTRSTZ, HDMI_I2CM_SOFTRSTZ_MASK, 0);
> +}
> +
> +static int hdmi_read_edid(struct dw_hdmi *hdmi, int block, u8 *buff)
> +{
> + int shift = (block % 2) * 0x80;
> + int edid_read_err = 0;
> + u32 trytime = 5;
> + u32 n;
> +
> + /* set ddc i2c clk which devided from ddc_clk to 100khz */
> + hdmi_write(hdmi, hdmi->i2c_clk_high, HDMI_I2CM_SS_SCL_HCNT_0_ADDR);
> + hdmi_write(hdmi, hdmi->i2c_clk_low, HDMI_I2CM_SS_SCL_LCNT_0_ADDR);
> + hdmi_mod(hdmi, HDMI_I2CM_DIV, HDMI_I2CM_DIV_FAST_STD_MODE,
> + HDMI_I2CM_DIV_STD_MODE);
> +
> + hdmi_write(hdmi, HDMI_I2CM_SLAVE_DDC_ADDR, HDMI_I2CM_SLAVE);
> + hdmi_write(hdmi, HDMI_I2CM_SEGADDR_DDC, HDMI_I2CM_SEGADDR);
> + hdmi_write(hdmi, block >> 1, HDMI_I2CM_SEGPTR);
> +
> + while (trytime--) {
> + edid_read_err = 0;
> +
> + for (n = 0; n < HDMI_EDID_BLOCK_SIZE; n++) {
> + hdmi_write(hdmi, shift + n, HDMI_I2CM_ADDRESS);
> +
> + if (block == 0)
> + hdmi_write(hdmi, HDMI_I2CM_OP_RD8,
> + HDMI_I2CM_OPERATION);
> + else
> + hdmi_write(hdmi, HDMI_I2CM_OP_RD8_EXT,
> + HDMI_I2CM_OPERATION);
> +
> + if (hdmi_ddc_wait_i2c_done(hdmi, 10)) {
> + hdmi_ddc_reset(hdmi);
> + edid_read_err = 1;
> + break;
> + }
> +
> + buff[n] = hdmi_read(hdmi, HDMI_I2CM_DATAI);
> + }
> +
> + if (!edid_read_err)
> + break;
> + }
> +
> + return edid_read_err;
> +}
> +
> +static const u8 pre_buf[] = {
> + 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00,
> + 0x04, 0x69, 0xfa, 0x23, 0xc8, 0x28, 0x01, 0x00,
> + 0x10, 0x17, 0x01, 0x03, 0x80, 0x33, 0x1d, 0x78,
> + 0x2a, 0xd9, 0x45, 0xa2, 0x55, 0x4d, 0xa0, 0x27,
> + 0x12, 0x50, 0x54, 0xb7, 0xef, 0x00, 0x71, 0x4f,
> + 0x81, 0x40, 0x81, 0x80, 0x95, 0x00, 0xb3, 0x00,
> + 0xd1, 0xc0, 0x81, 0xc0, 0x81, 0x00, 0x02, 0x3a,
> + 0x80, 0x18, 0x71, 0x38, 0x2d, 0x40, 0x58, 0x2c,
> + 0x45, 0x00, 0xfd, 0x1e, 0x11, 0x00, 0x00, 0x1e,
> + 0x00, 0x00, 0x00, 0xff, 0x00, 0x44, 0x34, 0x4c,
> + 0x4d, 0x54, 0x46, 0x30, 0x37, 0x35, 0x39, 0x37,
> + 0x36, 0x0a, 0x00, 0x00, 0x00, 0xfd, 0x00, 0x32,
> + 0x4b, 0x18, 0x53, 0x11, 0x00, 0x0a, 0x20, 0x20,
> + 0x20, 0x20, 0x20, 0x20, 0x00, 0x00, 0x00, 0xfc,
> + 0x00, 0x41, 0x53, 0x55, 0x53, 0x20, 0x56, 0x53,
> + 0x32, 0x33, 0x38, 0x0a, 0x20, 0x20, 0x01, 0xb0,
> + 0x02, 0x03, 0x22, 0x71, 0x4f, 0x01, 0x02, 0x03,
> + 0x11, 0x12, 0x13, 0x04, 0x14, 0x05, 0x0e, 0x0f,
> + 0x1d, 0x1e, 0x1f, 0x10, 0x23, 0x09, 0x17, 0x07,
> + 0x83, 0x01, 0x00, 0x00, 0x65, 0x03, 0x0c, 0x00,
> + 0x10, 0x00, 0x8c, 0x0a, 0xd0, 0x8a, 0x20, 0xe0,
> + 0x2d, 0x10, 0x10, 0x3e, 0x96, 0x00, 0xfd, 0x1e,
> + 0x11, 0x00, 0x00, 0x18, 0x01, 0x1d, 0x00, 0x72,
> + 0x51, 0xd0, 0x1e, 0x20, 0x6e, 0x28, 0x55, 0x00,
> + 0xfd, 0x1e, 0x11, 0x00, 0x00, 0x1e, 0x01, 0x1d,
> + 0x00, 0xbc, 0x52, 0xd0, 0x1e, 0x20, 0xb8, 0x28,
> + 0x55, 0x40, 0xfd, 0x1e, 0x11, 0x00, 0x00, 0x1e,
> + 0x8c, 0x0a, 0xd0, 0x90, 0x20, 0x40, 0x31, 0x20,
> + 0x0c, 0x40, 0x55, 0x00, 0xfd, 0x1e, 0x11, 0x00,
> + 0x00, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe9,
> +};
> +
> +int dw_hdmi_phy_cfg(struct dw_hdmi *hdmi, uint mpixelclock)
> +{
> + int i, ret;
> +
> + /* hdmi phy spec says to do the phy initialization sequence twice */
> + for (i = 0; i < 2; i++) {
> + hdmi_phy_sel_data_en_pol(hdmi, 1);
> + hdmi_phy_sel_interface_control(hdmi, 0);
> + hdmi_phy_enable_tmds(hdmi, 0);
> + hdmi_phy_enable_power(hdmi, 0);
> +
> + ret = hdmi_phy_configure(hdmi, mpixelclock);
> + if (ret) {
> + debug("hdmi phy config failure %d\n", ret);
> + return ret;
> + }
> + }
> +
> + return 0;
> +}
> +
> +int dw_hdmi_phy_wait_for_hpd(struct dw_hdmi *hdmi)
> +{
> + ulong start;
> +
> + start = get_timer(0);
> + do {
> + if (hdmi_get_plug_in_status(hdmi))
> + return 0;
> + udelay(100);
> + } while (get_timer(start) < 300);
> +
> + return -1;
> +}
> +
> +void dw_hdmi_phy_init(struct dw_hdmi *hdmi)
> +{
> + /* enable phy i2cm done irq */
> + hdmi_write(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL,
> + HDMI_PHY_I2CM_INT_ADDR);
> +
> + /* enable phy i2cm nack & arbitration error irq */
> + hdmi_write(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL |
> + HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL,
> + HDMI_PHY_I2CM_CTLINT_ADDR);
> +
> + /* enable cable hot plug irq */
> + hdmi_write(hdmi, (u8)~HDMI_PHY_HPD, HDMI_PHY_MASK0);
> +
> + /* clear hotplug interrupts */
> + hdmi_write(hdmi, HDMI_IH_PHY_STAT0_HPD, HDMI_IH_PHY_STAT0);
> +}
> +
> +int dw_hdmi_read_edid(struct dw_hdmi *hdmi, u8 *buf, int buf_size)
> +{
> + u32 edid_size = HDMI_EDID_BLOCK_SIZE;
> + int ret;
> +
> + if (0) {
> + edid_size = sizeof(pre_buf);
> + memcpy(buf, pre_buf, edid_size);
> + } else {
> + ret = hdmi_read_edid(hdmi, 0, buf);
> + if (ret) {
> + debug("failed to read edid.\n");
> + return -1;
> + }
> +
> + if (buf[0x7e] != 0) {
> + hdmi_read_edid(hdmi, 1, buf + HDMI_EDID_BLOCK_SIZE);
> + edid_size += HDMI_EDID_BLOCK_SIZE;
> + }
> + }
> +
> + return edid_size;
> +}
> +
> +int dw_hdmi_enable(struct dw_hdmi *hdmi, const struct display_timing *edid)
> +{
> + int ret;
> +
> + debug("hdmi, mode info : clock %d hdis %d vdis %d\n",
> + edid->pixelclock.typ, edid->hactive.typ, edid->vactive.typ);
> +
> + hdmi_av_composer(hdmi, edid);
> +
> + ret = hdmi->phy_set(hdmi, edid->pixelclock.typ);
> + if (ret)
> + return ret;
> +
> + hdmi_enable_video_path(hdmi);
> +
> + hdmi_audio_fifo_reset(hdmi);
> + hdmi_audio_set_format(hdmi);
> + hdmi_audio_set_samplerate(hdmi, edid->pixelclock.typ);
> +
> + hdmi_video_packetize(hdmi);
> + hdmi_video_sample(hdmi);
> +
> + hdmi_clear_overflow(hdmi);
> +
> + return 0;
> +}
> +
> +void dw_hdmi_init(struct dw_hdmi *hdmi)
> +{
> + uint ih_mute;
> +
> + /*
> + * boot up defaults are:
> + * hdmi_ih_mute = 0x03 (disabled)
> + * hdmi_ih_mute_* = 0x00 (enabled)
> + *
> + * disable top level interrupt bits in hdmi block
> + */
> + ih_mute = /*hdmi_read(hdmi, HDMI_IH_MUTE) |*/
> + HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
> + HDMI_IH_MUTE_MUTE_ALL_INTERRUPT;
> +
> + hdmi_write(hdmi, ih_mute, HDMI_IH_MUTE);
> +
> + /* enable i2c master done irq */
> + hdmi_write(hdmi, ~0x04, HDMI_I2CM_INT);
> +
> + /* enable i2c client nack % arbitration error irq */
> + hdmi_write(hdmi, ~0x44, HDMI_I2CM_CTLINT);
> +}
> diff --git a/drivers/video/rockchip/Makefile b/drivers/video/rockchip/Makefile
> index 7962f8611e..755350b934 100644
> --- a/drivers/video/rockchip/Makefile
> +++ b/drivers/video/rockchip/Makefile
> @@ -5,4 +5,4 @@
> # SPDX-License-Identifier: GPL-2.0+
> #
>
> -obj-y += rk_edp.o rk_hdmi.o rk_vop.o rk_lvds.o
> +obj-y += rk_edp.o rk_hdmi.o rk_vop.o rk_lvds.o ../dw_hdmi.o
> diff --git a/drivers/video/rockchip/rk_hdmi.c b/drivers/video/rockchip/rk_hdmi.c
> index c8608db23c..db07588302 100644
> --- a/drivers/video/rockchip/rk_hdmi.c
> +++ b/drivers/video/rockchip/rk_hdmi.c
> @@ -9,6 +9,7 @@
> #include <clk.h>
> #include <display.h>
> #include <dm.h>
> +#include <dw_hdmi.h>
> #include <edid.h>
> #include <regmap.h>
> #include <syscon.h>
> @@ -16,73 +17,13 @@
> #include <asm/io.h>
> #include <asm/arch/clock.h>
> #include <asm/arch/grf_rk3288.h>
> -#include <asm/arch/hdmi_rk3288.h>
> #include <power/regulator.h>
>
> -struct tmds_n_cts {
> - u32 tmds;
> - u32 cts;
> - u32 n;
> -};
> -
> struct rk_hdmi_priv {
> - struct rk3288_hdmi *regs;
> + struct dw_hdmi hdmi;
> struct rk3288_grf *grf;
> };
>
> -static const struct tmds_n_cts n_cts_table[] = {
> - {
> - .tmds = 25175000, .n = 6144, .cts = 25175,
> - }, {
> - .tmds = 25200000, .n = 6144, .cts = 25200,
> - }, {
> - .tmds = 27000000, .n = 6144, .cts = 27000,
> - }, {
> - .tmds = 27027000, .n = 6144, .cts = 27027,
> - }, {
> - .tmds = 40000000, .n = 6144, .cts = 40000,
> - }, {
> - .tmds = 54000000, .n = 6144, .cts = 54000,
> - }, {
> - .tmds = 54054000, .n = 6144, .cts = 54054,
> - }, {
> - .tmds = 65000000, .n = 6144, .cts = 65000,
> - }, {
> - .tmds = 74176000, .n = 11648, .cts = 140625,
> - }, {
> - .tmds = 74250000, .n = 6144, .cts = 74250,
> - }, {
> - .tmds = 83500000, .n = 6144, .cts = 83500,
> - }, {
> - .tmds = 106500000, .n = 6144, .cts = 106500,
> - }, {
> - .tmds = 108000000, .n = 6144, .cts = 108000,
> - }, {
> - .tmds = 148352000, .n = 5824, .cts = 140625,
> - }, {
> - .tmds = 148500000, .n = 6144, .cts = 148500,
> - }, {
> - .tmds = 297000000, .n = 5120, .cts = 247500,
> - }
> -};
> -
> -struct hdmi_mpll_config {
> - u64 mpixelclock;
> - /* Mode of Operation and PLL Dividers Control Register */
> - u32 cpce;
> - /* PLL Gmp Control Register */
> - u32 gmp;
> - /* PLL Current COntrol Register */
> - u32 curr;
> -};
> -
> -struct hdmi_phy_config {
> - u64 mpixelclock;
> - u32 sym_ctr; /* clock symbol and transmitter control */
> - u32 term; /* transmission termination value */
> - u32 vlev_ctr; /* voltage level control */
> -};
> -
> static const struct hdmi_phy_config rockchip_phy_config[] = {
> {
> .mpixelclock = 74250000,
> @@ -124,693 +65,41 @@ static const struct hdmi_mpll_config rockchip_mpll_cfg[] = {
> }
> };
>
> -static void hdmi_set_clock_regenerator(struct rk3288_hdmi *regs, u32 n, u32 cts)
> -{
> - uint cts3;
> - uint n3;
> -
> - /* first set ncts_atomic_write (if present) */
> - n3 = HDMI_AUD_N3_NCTS_ATOMIC_WRITE;
> - writel(n3, ®s->aud_n3);
> -
> - /* set cts_manual (if present) */
> - cts3 = HDMI_AUD_CTS3_CTS_MANUAL;
> -
> - cts3 |= HDMI_AUD_CTS3_N_SHIFT_1 << HDMI_AUD_CTS3_N_SHIFT_OFFSET;
> - cts3 |= (cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK;
> -
> - /* write cts values; cts3 must be written first */
> - writel(cts3, ®s->aud_cts3);
> - writel((cts >> 8) & 0xff, ®s->aud_cts2);
> - writel(cts & 0xff, ®s->aud_cts1);
> -
> - /* write n values; n1 must be written last */
> - n3 |= (n >> 16) & HDMI_AUD_N3_AUDN19_16_MASK;
> - writel(n3, ®s->aud_n3);
> - writel((n >> 8) & 0xff, ®s->aud_n2);
> - writel(n & 0xff, ®s->aud_n1);
> -
> - writel(HDMI_AUD_INPUTCLKFS_128, ®s->aud_inputclkfs);
> -}
> -
> -static int hdmi_lookup_n_cts(u32 pixel_clk)
> -{
> - int i;
> -
> - for (i = 0; i < ARRAY_SIZE(n_cts_table); i++)
> - if (pixel_clk <= n_cts_table[i].tmds)
> - break;
> -
> - if (i >= ARRAY_SIZE(n_cts_table))
> - return -1;
> -
> - return i;
> -}
> -
> -static void hdmi_audio_set_samplerate(struct rk3288_hdmi *regs, u32 pixel_clk)
> -{
> - u32 clk_n, clk_cts;
> - int index;
> -
> - index = hdmi_lookup_n_cts(pixel_clk);
> - if (index == -1) {
> - debug("audio not supported for pixel clk %d\n", pixel_clk);
> - return;
> - }
> -
> - clk_n = n_cts_table[index].n;
> - clk_cts = n_cts_table[index].cts;
> - hdmi_set_clock_regenerator(regs, clk_n, clk_cts);
> -}
> -
> -/*
> - * this submodule is responsible for the video data synchronization.
> - * for example, for rgb 4:4:4 input, the data map is defined as
> - * pin{47~40} <==> r[7:0]
> - * pin{31~24} <==> g[7:0]
> - * pin{15~8} <==> b[7:0]
> - */
> -static void hdmi_video_sample(struct rk3288_hdmi *regs)
> -{
> - u32 color_format = 0x01;
> - uint val;
> -
> - val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE |
> - ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) &
> - HDMI_TX_INVID0_VIDEO_MAPPING_MASK);
> -
> - writel(val, ®s->tx_invid0);
> -
> - /* enable tx stuffing: when de is inactive, fix the output data to 0 */
> - val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE |
> - HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE |
> - HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE;
> - writel(val, ®s->tx_instuffing);
> - writel(0x0, ®s->tx_gydata0);
> - writel(0x0, ®s->tx_gydata1);
> - writel(0x0, ®s->tx_rcrdata0);
> - writel(0x0, ®s->tx_rcrdata1);
> - writel(0x0, ®s->tx_bcbdata0);
> - writel(0x0, ®s->tx_bcbdata1);
> -}
> -
> -static void hdmi_video_packetize(struct rk3288_hdmi *regs)
> -{
> - u32 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
> - u32 remap_size = HDMI_VP_REMAP_YCC422_16BIT;
> - u32 color_depth = 0;
> - uint val, vp_conf;
> -
> - /* set the packetizer registers */
> - val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) &
> - HDMI_VP_PR_CD_COLOR_DEPTH_MASK) |
> - ((0 << HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) &
> - HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK);
> - writel(val, ®s->vp_pr_cd);
> -
> - clrsetbits_le32(®s->vp_stuff, HDMI_VP_STUFF_PR_STUFFING_MASK,
> - HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE);
> -
> - /* data from pixel repeater block */
> - vp_conf = HDMI_VP_CONF_PR_EN_DISABLE |
> - HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER;
> -
> - clrsetbits_le32(®s->vp_conf, HDMI_VP_CONF_PR_EN_MASK |
> - HDMI_VP_CONF_BYPASS_SELECT_MASK, vp_conf);
> -
> - clrsetbits_le32(®s->vp_stuff, HDMI_VP_STUFF_IDEFAULT_PHASE_MASK,
> - 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET);
> -
> - writel(remap_size, ®s->vp_remap);
> -
> - vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE |
> - HDMI_VP_CONF_PP_EN_DISABLE |
> - HDMI_VP_CONF_YCC422_EN_DISABLE;
> -
> - clrsetbits_le32(®s->vp_conf, HDMI_VP_CONF_BYPASS_EN_MASK |
> - HDMI_VP_CONF_PP_EN_ENMASK | HDMI_VP_CONF_YCC422_EN_MASK,
> - vp_conf);
> -
> - clrsetbits_le32(®s->vp_stuff, HDMI_VP_STUFF_PP_STUFFING_MASK |
> - HDMI_VP_STUFF_YCC422_STUFFING_MASK,
> - HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE |
> - HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE);
> -
> - clrsetbits_le32(®s->vp_conf, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK,
> - output_select);
> -}
> -
> -static inline void hdmi_phy_test_clear(struct rk3288_hdmi *regs, uint bit)
> -{
> - clrsetbits_le32(®s->phy_tst0, HDMI_PHY_TST0_TSTCLR_MASK,
> - bit << HDMI_PHY_TST0_TSTCLR_OFFSET);
> -}
> -
> -static int hdmi_phy_wait_i2c_done(struct rk3288_hdmi *regs, u32 msec)
> -{
> - ulong start;
> - u32 val;
> -
> - start = get_timer(0);
> - do {
> - val = readl(®s->ih_i2cmphy_stat0);
> - if (val & 0x3) {
> - writel(val, ®s->ih_i2cmphy_stat0);
> - return 0;
> - }
> -
> - udelay(100);
> - } while (get_timer(start) < msec);
> -
> - return 1;
> -}
> -
> -static void hdmi_phy_i2c_write(struct rk3288_hdmi *regs, uint data, uint addr)
> -{
> - writel(0xff, ®s->ih_i2cmphy_stat0);
> - writel(addr, ®s->phy_i2cm_address_addr);
> - writel((u8)(data >> 8), ®s->phy_i2cm_datao_1_addr);
> - writel((u8)(data >> 0), ®s->phy_i2cm_datao_0_addr);
> - writel(HDMI_PHY_I2CM_OPERATION_ADDR_WRITE,
> - ®s->phy_i2cm_operation_addr);
> -
> - hdmi_phy_wait_i2c_done(regs, 1000);
> -}
> -
> -static void hdmi_phy_enable_power(struct rk3288_hdmi *regs, uint enable)
> -{
> - clrsetbits_le32(®s->phy_conf0, HDMI_PHY_CONF0_PDZ_MASK,
> - enable << HDMI_PHY_CONF0_PDZ_OFFSET);
> -}
> -
> -static void hdmi_phy_enable_tmds(struct rk3288_hdmi *regs, uint enable)
> -{
> - clrsetbits_le32(®s->phy_conf0, HDMI_PHY_CONF0_ENTMDS_MASK,
> - enable << HDMI_PHY_CONF0_ENTMDS_OFFSET);
> -}
> -
> -static void hdmi_phy_enable_spare(struct rk3288_hdmi *regs, uint enable)
> -{
> - clrsetbits_le32(®s->phy_conf0, HDMI_PHY_CONF0_SPARECTRL_MASK,
> - enable << HDMI_PHY_CONF0_SPARECTRL_OFFSET);
> -}
> -
> -static void hdmi_phy_gen2_pddq(struct rk3288_hdmi *regs, uint enable)
> -{
> - clrsetbits_le32(®s->phy_conf0, HDMI_PHY_CONF0_GEN2_PDDQ_MASK,
> - enable << HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET);
> -}
> -
> -static void hdmi_phy_gen2_txpwron(struct rk3288_hdmi *regs, uint enable)
> -{
> - clrsetbits_le32(®s->phy_conf0,
> - HDMI_PHY_CONF0_GEN2_TXPWRON_MASK,
> - enable << HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET);
> -}
> -
> -static void hdmi_phy_sel_data_en_pol(struct rk3288_hdmi *regs, uint enable)
> -{
> - clrsetbits_le32(®s->phy_conf0,
> - HDMI_PHY_CONF0_SELDATAENPOL_MASK,
> - enable << HDMI_PHY_CONF0_SELDATAENPOL_OFFSET);
> -}
> -
> -static void hdmi_phy_sel_interface_control(struct rk3288_hdmi *regs,
> - uint enable)
> -{
> - clrsetbits_le32(®s->phy_conf0, HDMI_PHY_CONF0_SELDIPIF_MASK,
> - enable << HDMI_PHY_CONF0_SELDIPIF_OFFSET);
> -}
> -
> -static int hdmi_phy_configure(struct rk3288_hdmi *regs, u32 mpixelclock)
> -{
> - ulong start;
> - uint i, val;
> -
> - writel(HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS,
> - ®s->mc_flowctrl);
> -
> - /* gen2 tx power off */
> - hdmi_phy_gen2_txpwron(regs, 0);
> -
> - /* gen2 pddq */
> - hdmi_phy_gen2_pddq(regs, 1);
> -
> - /* phy reset */
> - writel(HDMI_MC_PHYRSTZ_DEASSERT, ®s->mc_phyrstz);
> - writel(HDMI_MC_PHYRSTZ_ASSERT, ®s->mc_phyrstz);
> - writel(HDMI_MC_HEACPHY_RST_ASSERT, ®s->mc_heacphy_rst);
> -
> - hdmi_phy_test_clear(regs, 1);
> - writel(HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2, ®s->phy_i2cm_slave_addr);
> - hdmi_phy_test_clear(regs, 0);
> -
> - /* pll/mpll cfg - always match on final entry */
> - for (i = 0; rockchip_mpll_cfg[i].mpixelclock != (~0ul); i++)
> - if (mpixelclock <= rockchip_mpll_cfg[i].mpixelclock)
> - break;
> -
> - hdmi_phy_i2c_write(regs, rockchip_mpll_cfg[i].cpce, PHY_OPMODE_PLLCFG);
> - hdmi_phy_i2c_write(regs, rockchip_mpll_cfg[i].gmp, PHY_PLLGMPCTRL);
> - hdmi_phy_i2c_write(regs, rockchip_mpll_cfg[i].curr, PHY_PLLCURRCTRL);
> -
> - hdmi_phy_i2c_write(regs, 0x0000, PHY_PLLPHBYCTRL);
> - hdmi_phy_i2c_write(regs, 0x0006, PHY_PLLCLKBISTPHASE);
> -
> - for (i = 0; rockchip_phy_config[i].mpixelclock != (~0ul); i++)
> - if (mpixelclock <= rockchip_phy_config[i].mpixelclock)
> - break;
> -
> - /*
> - * resistance term 133ohm cfg
> - * preemp cgf 0.00
> - * tx/ck lvl 10
> - */
> - hdmi_phy_i2c_write(regs, rockchip_phy_config[i].term, PHY_TXTERM);
> - hdmi_phy_i2c_write(regs, rockchip_phy_config[i].sym_ctr,
> - PHY_CKSYMTXCTRL);
> - hdmi_phy_i2c_write(regs, rockchip_phy_config[i].vlev_ctr, PHY_VLEVCTRL);
> -
> - /* remove clk term */
> - hdmi_phy_i2c_write(regs, 0x8000, PHY_CKCALCTRL);
> -
> - hdmi_phy_enable_power(regs, 1);
> -
> - /* toggle tmds enable */
> - hdmi_phy_enable_tmds(regs, 0);
> - hdmi_phy_enable_tmds(regs, 1);
> -
> - /* gen2 tx power on */
> - hdmi_phy_gen2_txpwron(regs, 1);
> - hdmi_phy_gen2_pddq(regs, 0);
> -
> - hdmi_phy_enable_spare(regs, 1);
> -
> - /* wait for phy pll lock */
> - start = get_timer(0);
> - do {
> - val = readl(®s->phy_stat0);
> - if (!(val & HDMI_PHY_TX_PHY_LOCK))
> - return 0;
> -
> - udelay(100);
> - } while (get_timer(start) < 5);
> -
> - return -1;
> -}
> -
> -static int hdmi_phy_init(struct rk3288_hdmi *regs, uint mpixelclock)
> -{
> - int i, ret;
> -
> - /* hdmi phy spec says to do the phy initialization sequence twice */
> - for (i = 0; i < 2; i++) {
> - hdmi_phy_sel_data_en_pol(regs, 1);
> - hdmi_phy_sel_interface_control(regs, 0);
> - hdmi_phy_enable_tmds(regs, 0);
> - hdmi_phy_enable_power(regs, 0);
> -
> - ret = hdmi_phy_configure(regs, mpixelclock);
> - if (ret) {
> - debug("hdmi phy config failure %d\n", ret);
> - return ret;
> - }
> - }
> -
> - return 0;
> -}
> -
> -static void hdmi_av_composer(struct rk3288_hdmi *regs,
> - const struct display_timing *edid)
> -{
> - bool mdataenablepolarity = true;
> - uint inv_val;
> - uint hbl;
> - uint vbl;
> -
> - hbl = edid->hback_porch.typ + edid->hfront_porch.typ +
> - edid->hsync_len.typ;
> - vbl = edid->vback_porch.typ + edid->vfront_porch.typ +
> - edid->vsync_len.typ;
> -
> - /* set up hdmi_fc_invidconf */
> - inv_val = HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE;
> -
> - inv_val |= (edid->flags & DISPLAY_FLAGS_HSYNC_HIGH ?
> - HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH :
> - HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW);
> -
> - inv_val |= (edid->flags & DISPLAY_FLAGS_VSYNC_HIGH ?
> - HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH :
> - HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW);
> -
> - inv_val |= (mdataenablepolarity ?
> - HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH :
> - HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW);
> -
> - /*
> - * TODO(sjg at chromium.org>: Need to check for HDMI / DVI
> - * inv_val |= (edid->hdmi_monitor_detected ?
> - * HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE :
> - * HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE);
> - */
> - inv_val |= HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE;
> -
> - inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW;
> -
> - inv_val |= HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE;
> -
> - writel(inv_val, ®s->fc_invidconf);
> -
> - /* set up horizontal active pixel width */
> - writel(edid->hactive.typ >> 8, ®s->fc_inhactv1);
> - writel(edid->hactive.typ, ®s->fc_inhactv0);
> -
> - /* set up vertical active lines */
> - writel(edid->vactive.typ >> 8, ®s->fc_invactv1);
> - writel(edid->vactive.typ, ®s->fc_invactv0);
> -
> - /* set up horizontal blanking pixel region width */
> - writel(hbl >> 8, ®s->fc_inhblank1);
> - writel(hbl, ®s->fc_inhblank0);
> -
> - /* set up vertical blanking pixel region width */
> - writel(vbl, ®s->fc_invblank);
> -
> - /* set up hsync active edge delay width (in pixel clks) */
> - writel(edid->hfront_porch.typ >> 8, ®s->fc_hsyncindelay1);
> - writel(edid->hfront_porch.typ, ®s->fc_hsyncindelay0);
> -
> - /* set up vsync active edge delay (in lines) */
> - writel(edid->vfront_porch.typ, ®s->fc_vsyncindelay);
> -
> - /* set up hsync active pulse width (in pixel clks) */
> - writel(edid->hsync_len.typ >> 8, ®s->fc_hsyncinwidth1);
> - writel(edid->hsync_len.typ, ®s->fc_hsyncinwidth0);
> -
> - /* set up vsync active edge delay (in lines) */
> - writel(edid->vsync_len.typ, ®s->fc_vsyncinwidth);
> -}
> -
> -/* hdmi initialization step b.4 */
> -static void hdmi_enable_video_path(struct rk3288_hdmi *regs)
> -{
> - uint clkdis;
> -
> - /* control period minimum duration */
> - writel(12, ®s->fc_ctrldur);
> - writel(32, ®s->fc_exctrldur);
> - writel(1, ®s->fc_exctrlspac);
> -
> - /* set to fill tmds data channels */
> - writel(0x0b, ®s->fc_ch0pream);
> - writel(0x16, ®s->fc_ch1pream);
> - writel(0x21, ®s->fc_ch2pream);
> -
> - /* enable pixel clock and tmds data path */
> - clkdis = 0x7f;
> - clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE;
> - writel(clkdis, ®s->mc_clkdis);
> -
> - clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
> - writel(clkdis, ®s->mc_clkdis);
> -
> - clkdis &= ~HDMI_MC_CLKDIS_AUDCLK_DISABLE;
> - writel(clkdis, ®s->mc_clkdis);
> -}
> -
> -/* workaround to clear the overflow condition */
> -static void hdmi_clear_overflow(struct rk3288_hdmi *regs)
> -{
> - uint val, count;
> -
> - /* tmds software reset */
> - writel((u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, ®s->mc_swrstz);
> -
> - val = readl(®s->fc_invidconf);
> -
> - for (count = 0; count < 4; count++)
> - writel(val, ®s->fc_invidconf);
> -}
> -
> -static void hdmi_audio_set_format(struct rk3288_hdmi *regs)
> -{
> - writel(HDMI_AUD_CONF0_I2S_SELECT | HDMI_AUD_CONF0_I2S_IN_EN_0,
> - ®s->aud_conf0);
> -
> -
> - writel(HDMI_AUD_CONF1_I2S_MODE_STANDARD_MODE |
> - HDMI_AUD_CONF1_I2S_WIDTH_16BIT, ®s->aud_conf1);
> -
> - writel(0x00, ®s->aud_conf2);
> -}
> -
> -static void hdmi_audio_fifo_reset(struct rk3288_hdmi *regs)
> -{
> - writel((u8)~HDMI_MC_SWRSTZ_II2SSWRST_REQ, ®s->mc_swrstz);
> - writel(HDMI_AUD_CONF0_SW_AUDIO_FIFO_RST, ®s->aud_conf0);
> -
> - writel(0x00, ®s->aud_int);
> - writel(0x00, ®s->aud_int1);
> -}
> -
> -static void hdmi_init_interrupt(struct rk3288_hdmi *regs)
> -{
> - uint ih_mute;
> -
> - /*
> - * boot up defaults are:
> - * hdmi_ih_mute = 0x03 (disabled)
> - * hdmi_ih_mute_* = 0x00 (enabled)
> - *
> - * disable top level interrupt bits in hdmi block
> - */
> - ih_mute = readl(®s->ih_mute) |
> - HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
> - HDMI_IH_MUTE_MUTE_ALL_INTERRUPT;
> -
> - writel(ih_mute, ®s->ih_mute);
> -
> - /* enable i2c master done irq */
> - writel(~0x04, ®s->i2cm_int);
> -
> - /* enable i2c client nack % arbitration error irq */
> - writel(~0x44, ®s->i2cm_ctlint);
> -
> - /* enable phy i2cm done irq */
> - writel(HDMI_PHY_I2CM_INT_ADDR_DONE_POL, ®s->phy_i2cm_int_addr);
> -
> - /* enable phy i2cm nack & arbitration error irq */
> - writel(HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL |
> - HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL,
> - ®s->phy_i2cm_ctlint_addr);
> -
> - /* enable cable hot plug irq */
> - writel((u8)~HDMI_PHY_HPD, ®s->phy_mask0);
> -
> - /* clear hotplug interrupts */
> - writel(HDMI_IH_PHY_STAT0_HPD, ®s->ih_phy_stat0);
> -}
> -
> -static int hdmi_get_plug_in_status(struct rk3288_hdmi *regs)
> -{
> - uint val = readl(®s->phy_stat0) & HDMI_PHY_HPD;
> -
> - return !!val;
> -}
> -
> -static int hdmi_wait_for_hpd(struct rk3288_hdmi *regs)
> -{
> - ulong start;
> -
> - start = get_timer(0);
> - do {
> - if (hdmi_get_plug_in_status(regs))
> - return 0;
> - udelay(100);
> - } while (get_timer(start) < 300);
> -
> - return -1;
> -}
> -
> -static int hdmi_ddc_wait_i2c_done(struct rk3288_hdmi *regs, int msec)
> -{
> - u32 val;
> - ulong start;
> -
> - start = get_timer(0);
> - do {
> - val = readl(®s->ih_i2cm_stat0);
> - if (val & 0x2) {
> - writel(val, ®s->ih_i2cm_stat0);
> - return 0;
> - }
> -
> - udelay(100);
> - } while (get_timer(start) < msec);
> -
> - return 1;
> -}
> -
> -static void hdmi_ddc_reset(struct rk3288_hdmi *regs)
> -{
> - clrbits_le32(®s->i2cm_softrstz, HDMI_I2CM_SOFTRSTZ);
> -}
> -
> -static int hdmi_read_edid(struct rk3288_hdmi *regs, int block, u8 *buff)
> -{
> - int shift = (block % 2) * 0x80;
> - int edid_read_err = 0;
> - u32 trytime = 5;
> - u32 n, j, val;
> -
> - /* set ddc i2c clk which devided from ddc_clk to 100khz */
> - writel(0x7a, ®s->i2cm_ss_scl_hcnt_0_addr);
> - writel(0x8d, ®s->i2cm_ss_scl_lcnt_0_addr);
> -
> - /*
> - * TODO(sjg at chromium.org): The above values don't work - these ones
> - * work better, but generate lots of errors in the data.
> - */
> - writel(0x0d, ®s->i2cm_ss_scl_hcnt_0_addr);
> - writel(0x0d, ®s->i2cm_ss_scl_lcnt_0_addr);
> - clrsetbits_le32(®s->i2cm_div, HDMI_I2CM_DIV_FAST_STD_MODE,
> - HDMI_I2CM_DIV_STD_MODE);
> -
> - writel(HDMI_I2CM_SLAVE_DDC_ADDR, ®s->i2cm_slave);
> - writel(HDMI_I2CM_SEGADDR_DDC, ®s->i2cm_segaddr);
> - writel(block >> 1, ®s->i2cm_segptr);
> -
> - while (trytime--) {
> - edid_read_err = 0;
> -
> - for (n = 0; n < HDMI_EDID_BLOCK_SIZE / 8; n++) {
> - writel(shift + 8 * n, ®s->i2c_address);
> -
> - if (block == 0)
> - clrsetbits_le32(®s->i2cm_operation,
> - HDMI_I2CM_OPT_RD8,
> - HDMI_I2CM_OPT_RD8);
> - else
> - clrsetbits_le32(®s->i2cm_operation,
> - HDMI_I2CM_OPT_RD8_EXT,
> - HDMI_I2CM_OPT_RD8_EXT);
> -
> - if (hdmi_ddc_wait_i2c_done(regs, 10)) {
> - hdmi_ddc_reset(regs);
> - edid_read_err = 1;
> - break;
> - }
> -
> - for (j = 0; j < 8; j++) {
> - val = readl(®s->i2cm_buf0 + j);
> - buff[8 * n + j] = val;
> - }
> - }
> -
> - if (!edid_read_err)
> - break;
> - }
> -
> - return edid_read_err;
> -}
> -
> -static const u8 pre_buf[] = {
> - 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00,
> - 0x04, 0x69, 0xfa, 0x23, 0xc8, 0x28, 0x01, 0x00,
> - 0x10, 0x17, 0x01, 0x03, 0x80, 0x33, 0x1d, 0x78,
> - 0x2a, 0xd9, 0x45, 0xa2, 0x55, 0x4d, 0xa0, 0x27,
> - 0x12, 0x50, 0x54, 0xb7, 0xef, 0x00, 0x71, 0x4f,
> - 0x81, 0x40, 0x81, 0x80, 0x95, 0x00, 0xb3, 0x00,
> - 0xd1, 0xc0, 0x81, 0xc0, 0x81, 0x00, 0x02, 0x3a,
> - 0x80, 0x18, 0x71, 0x38, 0x2d, 0x40, 0x58, 0x2c,
> - 0x45, 0x00, 0xfd, 0x1e, 0x11, 0x00, 0x00, 0x1e,
> - 0x00, 0x00, 0x00, 0xff, 0x00, 0x44, 0x34, 0x4c,
> - 0x4d, 0x54, 0x46, 0x30, 0x37, 0x35, 0x39, 0x37,
> - 0x36, 0x0a, 0x00, 0x00, 0x00, 0xfd, 0x00, 0x32,
> - 0x4b, 0x18, 0x53, 0x11, 0x00, 0x0a, 0x20, 0x20,
> - 0x20, 0x20, 0x20, 0x20, 0x00, 0x00, 0x00, 0xfc,
> - 0x00, 0x41, 0x53, 0x55, 0x53, 0x20, 0x56, 0x53,
> - 0x32, 0x33, 0x38, 0x0a, 0x20, 0x20, 0x01, 0xb0,
> - 0x02, 0x03, 0x22, 0x71, 0x4f, 0x01, 0x02, 0x03,
> - 0x11, 0x12, 0x13, 0x04, 0x14, 0x05, 0x0e, 0x0f,
> - 0x1d, 0x1e, 0x1f, 0x10, 0x23, 0x09, 0x17, 0x07,
> - 0x83, 0x01, 0x00, 0x00, 0x65, 0x03, 0x0c, 0x00,
> - 0x10, 0x00, 0x8c, 0x0a, 0xd0, 0x8a, 0x20, 0xe0,
> - 0x2d, 0x10, 0x10, 0x3e, 0x96, 0x00, 0xfd, 0x1e,
> - 0x11, 0x00, 0x00, 0x18, 0x01, 0x1d, 0x00, 0x72,
> - 0x51, 0xd0, 0x1e, 0x20, 0x6e, 0x28, 0x55, 0x00,
> - 0xfd, 0x1e, 0x11, 0x00, 0x00, 0x1e, 0x01, 0x1d,
> - 0x00, 0xbc, 0x52, 0xd0, 0x1e, 0x20, 0xb8, 0x28,
> - 0x55, 0x40, 0xfd, 0x1e, 0x11, 0x00, 0x00, 0x1e,
> - 0x8c, 0x0a, 0xd0, 0x90, 0x20, 0x40, 0x31, 0x20,
> - 0x0c, 0x40, 0x55, 0x00, 0xfd, 0x1e, 0x11, 0x00,
> - 0x00, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe9,
> -};
> -
> static int rk_hdmi_read_edid(struct udevice *dev, u8 *buf, int buf_size)
> {
> struct rk_hdmi_priv *priv = dev_get_priv(dev);
> - u32 edid_size = HDMI_EDID_BLOCK_SIZE;
> - int ret;
> -
> - if (0) {
> - edid_size = sizeof(pre_buf);
> - memcpy(buf, pre_buf, edid_size);
> - } else {
> - ret = hdmi_read_edid(priv->regs, 0, buf);
> - if (ret) {
> - debug("failed to read edid.\n");
> - return -1;
> - }
>
> - if (buf[0x7e] != 0) {
> - hdmi_read_edid(priv->regs, 1,
> - buf + HDMI_EDID_BLOCK_SIZE);
> - edid_size += HDMI_EDID_BLOCK_SIZE;
> - }
> - }
> -
> - return edid_size;
> + return dw_hdmi_read_edid(&priv->hdmi, buf, buf_size);
> }
>
> static int rk_hdmi_enable(struct udevice *dev, int panel_bpp,
> const struct display_timing *edid)
> {
> struct rk_hdmi_priv *priv = dev_get_priv(dev);
> - struct rk3288_hdmi *regs = priv->regs;
> - int ret;
> -
> - debug("hdmi, mode info : clock %d hdis %d vdis %d\n",
> - edid->pixelclock.typ, edid->hactive.typ, edid->vactive.typ);
>
> - hdmi_av_composer(regs, edid);
> -
> - ret = hdmi_phy_init(regs, edid->pixelclock.typ);
> - if (ret)
> - return ret;
> -
> - hdmi_enable_video_path(regs);
> -
> - hdmi_audio_fifo_reset(regs);
> - hdmi_audio_set_format(regs);
> - hdmi_audio_set_samplerate(regs, edid->pixelclock.typ);
> -
> - hdmi_video_packetize(regs);
> - hdmi_video_sample(regs);
> -
> - hdmi_clear_overflow(regs);
> -
> - return 0;
> + return dw_hdmi_enable(&priv->hdmi, edid);
> }
>
> static int rk_hdmi_ofdata_to_platdata(struct udevice *dev)
> {
> struct rk_hdmi_priv *priv = dev_get_priv(dev);
> + struct dw_hdmi *hdmi = &priv->hdmi;
> +
> + hdmi->ioaddr = (ulong)dev_get_addr(dev);
> + hdmi->mpll_cfg = rockchip_mpll_cfg;
> + hdmi->phy_cfg = rockchip_phy_config;
> + hdmi->i2c_clk_high = 0x7a;
> + hdmi->i2c_clk_low = 0x8d;
> +
> + /*
> + * TODO(sjg at chromium.org): The above values don't work - these ones
> + * work better, but generate lots of errors in the data.
> + */
> + hdmi->i2c_clk_high = 0x0d;
> + hdmi->i2c_clk_low = 0x0d;
> + hdmi->reg_io_width = 4;
> + hdmi->phy_set = dw_hdmi_phy_cfg;
>
> - priv->regs = (struct rk3288_hdmi *)dev_get_addr(dev);
> priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
>
> return 0;
> @@ -820,6 +109,7 @@ static int rk_hdmi_probe(struct udevice *dev)
> {
> struct display_plat *uc_plat = dev_get_uclass_platdata(dev);
> struct rk_hdmi_priv *priv = dev_get_priv(dev);
> + struct dw_hdmi *hdmi = &priv->hdmi;
> struct udevice *reg;
> struct clk clk;
> int ret;
> @@ -863,13 +153,14 @@ static int rk_hdmi_probe(struct udevice *dev)
> rk_clrsetreg(&priv->grf->soc_con6, 1 << 4,
> (vop_id == 1) ? (1 << 4) : 0);
>
> - ret = hdmi_wait_for_hpd(priv->regs);
> + ret = dw_hdmi_phy_wait_for_hpd(hdmi);
> if (ret < 0) {
> debug("hdmi can not get hpd signal\n");
> return -1;
> }
>
> - hdmi_init_interrupt(priv->regs);
> + dw_hdmi_init(hdmi);
> + dw_hdmi_phy_init(hdmi);
>
> return 0;
> }
> diff --git a/drivers/video/rockchip/rk_vop.c b/drivers/video/rockchip/rk_vop.c
> index aeecb5815b..bc02f800dc 100644
> --- a/drivers/video/rockchip/rk_vop.c
> +++ b/drivers/video/rockchip/rk_vop.c
> @@ -20,7 +20,6 @@
> #include <asm/arch/cru_rk3288.h>
> #include <asm/arch/grf_rk3288.h>
> #include <asm/arch/edp_rk3288.h>
> -#include <asm/arch/hdmi_rk3288.h>
> #include <asm/arch/vop_rk3288.h>
> #include <dm/device-internal.h>
> #include <dm/uclass-internal.h>
> diff --git a/include/dw_hdmi.h b/include/dw_hdmi.h
> new file mode 100644
> index 0000000000..902abd4d44
> --- /dev/null
> +++ b/include/dw_hdmi.h
> @@ -0,0 +1,486 @@
> +/*
> + * Copyright (c) 2015 Google, Inc
> + * Copyright 2014 Rockchip Inc.
> + * Copyright (C) 2011 Freescale Semiconductor, Inc.
> + * (C) Copyright 2017 Jernej Skrabec <jernej.skrabec at siol.net>
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#ifndef _DW_HDMI_H
> +#define _DW_HDMI_H
> +
> +#include <edid.h>
> +
> +#define HDMI_EDID_BLOCK_SIZE 128
> +
> +/* Identification Registers */
> +#define HDMI_DESIGN_ID 0x0000
> +#define HDMI_REVISION_ID 0x0001
> +#define HDMI_PRODUCT_ID0 0x0002
> +#define HDMI_PRODUCT_ID1 0x0003
> +#define HDMI_CONFIG0_ID 0x0004
> +#define HDMI_CONFIG1_ID 0x0005
> +#define HDMI_CONFIG2_ID 0x0006
> +#define HDMI_CONFIG3_ID 0x0007
> +
> +/* Interrupt Registers */
> +#define HDMI_IH_FC_STAT0 0x0100
> +#define HDMI_IH_FC_STAT1 0x0101
> +#define HDMI_IH_FC_STAT2 0x0102
> +#define HDMI_IH_AS_STAT0 0x0103
> +#define HDMI_IH_PHY_STAT0 0x0104
> +#define HDMI_IH_I2CM_STAT0 0x0105
> +#define HDMI_IH_CEC_STAT0 0x0106
> +#define HDMI_IH_VP_STAT0 0x0107
> +#define HDMI_IH_I2CMPHY_STAT0 0x0108
> +#define HDMI_IH_AHBDMAAUD_STAT0 0x0109
> +
> +#define HDMI_IH_MUTE_FC_STAT0 0x0180
> +#define HDMI_IH_MUTE_FC_STAT1 0x0181
> +#define HDMI_IH_MUTE_FC_STAT2 0x0182
> +#define HDMI_IH_MUTE_AS_STAT0 0x0183
> +#define HDMI_IH_MUTE_PHY_STAT0 0x0184
> +#define HDMI_IH_MUTE_I2CM_STAT0 0x0185
> +#define HDMI_IH_MUTE_CEC_STAT0 0x0186
> +#define HDMI_IH_MUTE_VP_STAT0 0x0187
> +#define HDMI_IH_MUTE_I2CMPHY_STAT0 0x0188
> +#define HDMI_IH_MUTE_AHBDMAAUD_STAT0 0x0189
> +#define HDMI_IH_MUTE 0x01FF
> +
> +/* Video Sample Registers */
> +#define HDMI_TX_INVID0 0x0200
> +#define HDMI_TX_INSTUFFING 0x0201
> +#define HDMI_TX_GYDATA0 0x0202
> +#define HDMI_TX_GYDATA1 0x0203
> +#define HDMI_TX_RCRDATA0 0x0204
> +#define HDMI_TX_RCRDATA1 0x0205
> +#define HDMI_TX_BCBDATA0 0x0206
> +#define HDMI_TX_BCBDATA1 0x0207
> +
> +/* Video Packetizer Registers */
> +#define HDMI_VP_STATUS 0x0800
> +#define HDMI_VP_PR_CD 0x0801
> +#define HDMI_VP_STUFF 0x0802
> +#define HDMI_VP_REMAP 0x0803
> +#define HDMI_VP_CONF 0x0804
> +#define HDMI_VP_STAT 0x0805
> +#define HDMI_VP_INT 0x0806
> +#define HDMI_VP_MASK 0x0807
> +#define HDMI_VP_POL 0x0808
> +
> +/* Frame Composer Registers */
> +#define HDMI_FC_INVIDCONF 0x1000
> +#define HDMI_FC_INHACTV0 0x1001
> +#define HDMI_FC_INHACTV1 0x1002
> +#define HDMI_FC_INHBLANK0 0x1003
> +#define HDMI_FC_INHBLANK1 0x1004
> +#define HDMI_FC_INVACTV0 0x1005
> +#define HDMI_FC_INVACTV1 0x1006
> +#define HDMI_FC_INVBLANK 0x1007
> +#define HDMI_FC_HSYNCINDELAY0 0x1008
> +#define HDMI_FC_HSYNCINDELAY1 0x1009
> +#define HDMI_FC_HSYNCINWIDTH0 0x100A
> +#define HDMI_FC_HSYNCINWIDTH1 0x100B
> +#define HDMI_FC_VSYNCINDELAY 0x100C
> +#define HDMI_FC_VSYNCINWIDTH 0x100D
> +#define HDMI_FC_INFREQ0 0x100E
> +#define HDMI_FC_INFREQ1 0x100F
> +#define HDMI_FC_INFREQ2 0x1010
> +#define HDMI_FC_CTRLDUR 0x1011
> +#define HDMI_FC_EXCTRLDUR 0x1012
> +#define HDMI_FC_EXCTRLSPAC 0x1013
> +#define HDMI_FC_CH0PREAM 0x1014
> +#define HDMI_FC_CH1PREAM 0x1015
> +#define HDMI_FC_CH2PREAM 0x1016
> +#define HDMI_FC_AVICONF3 0x1017
> +#define HDMI_FC_GCP 0x1018
> +#define HDMI_FC_AVICONF0 0x1019
> +#define HDMI_FC_AVICONF1 0x101A
> +#define HDMI_FC_AVICONF2 0x101B
> +#define HDMI_FC_AVIVID 0x101C
> +#define HDMI_FC_AVIETB0 0x101D
> +#define HDMI_FC_AVIETB1 0x101E
> +#define HDMI_FC_AVISBB0 0x101F
> +#define HDMI_FC_AVISBB1 0x1020
> +#define HDMI_FC_AVIELB0 0x1021
> +#define HDMI_FC_AVIELB1 0x1022
> +#define HDMI_FC_AVISRB0 0x1023
> +#define HDMI_FC_AVISRB1 0x1024
> +#define HDMI_FC_AUDICONF0 0x1025
> +#define HDMI_FC_AUDICONF1 0x1026
> +#define HDMI_FC_AUDICONF2 0x1027
> +#define HDMI_FC_AUDICONF3 0x1028
> +#define HDMI_FC_VSDIEEEID0 0x1029
> +#define HDMI_FC_VSDSIZE 0x102A
> +
> +/* HDMI Source PHY Registers */
> +#define HDMI_PHY_CONF0 0x3000
> +#define HDMI_PHY_TST0 0x3001
> +#define HDMI_PHY_TST1 0x3002
> +#define HDMI_PHY_TST2 0x3003
> +#define HDMI_PHY_STAT0 0x3004
> +#define HDMI_PHY_INT0 0x3005
> +#define HDMI_PHY_MASK0 0x3006
> +#define HDMI_PHY_POL0 0x3007
> +
> +/* HDMI Master PHY Registers */
> +#define HDMI_PHY_I2CM_SLAVE_ADDR 0x3020
> +#define HDMI_PHY_I2CM_ADDRESS_ADDR 0x3021
> +#define HDMI_PHY_I2CM_DATAO_1_ADDR 0x3022
> +#define HDMI_PHY_I2CM_DATAO_0_ADDR 0x3023
> +#define HDMI_PHY_I2CM_DATAI_1_ADDR 0x3024
> +#define HDMI_PHY_I2CM_DATAI_0_ADDR 0x3025
> +#define HDMI_PHY_I2CM_OPERATION_ADDR 0x3026
> +#define HDMI_PHY_I2CM_INT_ADDR 0x3027
> +#define HDMI_PHY_I2CM_CTLINT_ADDR 0x3028
> +#define HDMI_PHY_I2CM_DIV_ADDR 0x3029
> +#define HDMI_PHY_I2CM_SOFTRSTZ_ADDR 0x302a
> +#define HDMI_PHY_I2CM_SS_SCL_HCNT_1_ADDR 0x302b
> +#define HDMI_PHY_I2CM_SS_SCL_HCNT_0_ADDR 0x302c
> +#define HDMI_PHY_I2CM_SS_SCL_LCNT_1_ADDR 0x302d
> +#define HDMI_PHY_I2CM_SS_SCL_LCNT_0_ADDR 0x302e
> +#define HDMI_PHY_I2CM_FS_SCL_HCNT_1_ADDR 0x302f
> +#define HDMI_PHY_I2CM_FS_SCL_HCNT_0_ADDR 0x3030
> +#define HDMI_PHY_I2CM_FS_SCL_LCNT_1_ADDR 0x3031
> +#define HDMI_PHY_I2CM_FS_SCL_LCNT_0_ADDR 0x3032
> +
> +/* Audio Sampler Registers */
> +#define HDMI_AUD_CONF0 0x3100
> +#define HDMI_AUD_CONF1 0x3101
> +#define HDMI_AUD_INT 0x3102
> +#define HDMI_AUD_CONF2 0x3103
> +#define HDMI_AUD_INT1 0x3104
> +#define HDMI_AUD_N1 0x3200
> +#define HDMI_AUD_N2 0x3201
> +#define HDMI_AUD_N3 0x3202
> +#define HDMI_AUD_CTS1 0x3203
> +#define HDMI_AUD_CTS2 0x3204
> +#define HDMI_AUD_CTS3 0x3205
> +#define HDMI_AUD_INPUTCLKFS 0x3206
> +#define HDMI_AUD_SPDIFINT 0x3302
> +#define HDMI_AUD_CONF0_HBR 0x3400
> +#define HDMI_AUD_HBR_STATUS 0x3401
> +#define HDMI_AUD_HBR_INT 0x3402
> +#define HDMI_AUD_HBR_POL 0x3403
> +#define HDMI_AUD_HBR_MASK 0x3404
> +
> +/* Main Controller Registers */
> +#define HDMI_MC_SFRDIV 0x4000
> +#define HDMI_MC_CLKDIS 0x4001
> +#define HDMI_MC_SWRSTZ 0x4002
> +#define HDMI_MC_OPCTRL 0x4003
> +#define HDMI_MC_FLOWCTRL 0x4004
> +#define HDMI_MC_PHYRSTZ 0x4005
> +#define HDMI_MC_LOCKONCLOCK 0x4006
> +#define HDMI_MC_HEACPHY_RST 0x4007
> +
> +/* I2C Master Registers (E-DDC) */
> +#define HDMI_I2CM_SLAVE 0x7E00
> +#define HDMI_I2CM_ADDRESS 0x7E01
> +#define HDMI_I2CM_DATAO 0x7E02
> +#define HDMI_I2CM_DATAI 0x7E03
> +#define HDMI_I2CM_OPERATION 0x7E04
> +#define HDMI_I2CM_INT 0x7E05
> +#define HDMI_I2CM_CTLINT 0x7E06
> +#define HDMI_I2CM_DIV 0x7E07
> +#define HDMI_I2CM_SEGADDR 0x7E08
> +#define HDMI_I2CM_SOFTRSTZ 0x7E09
> +#define HDMI_I2CM_SEGPTR 0x7E0A
> +#define HDMI_I2CM_SS_SCL_HCNT_1_ADDR 0x7E0B
> +#define HDMI_I2CM_SS_SCL_HCNT_0_ADDR 0x7E0C
> +#define HDMI_I2CM_SS_SCL_LCNT_1_ADDR 0x7E0D
> +#define HDMI_I2CM_SS_SCL_LCNT_0_ADDR 0x7E0E
> +#define HDMI_I2CM_FS_SCL_HCNT_1_ADDR 0x7E0F
> +#define HDMI_I2CM_FS_SCL_HCNT_0_ADDR 0x7E10
> +#define HDMI_I2CM_FS_SCL_LCNT_1_ADDR 0x7E11
> +#define HDMI_I2CM_FS_SCL_LCNT_0_ADDR 0x7E12
> +#define HDMI_I2CM_BUF0 0x7E20
> +
> +enum {
> + /* HDMI PHY registers define */
> + PHY_OPMODE_PLLCFG = 0x06,
> + PHY_CKCALCTRL = 0x05,
> + PHY_CKSYMTXCTRL = 0x09,
> + PHY_VLEVCTRL = 0x0e,
> + PHY_PLLCURRCTRL = 0x10,
> + PHY_PLLPHBYCTRL = 0x13,
> + PHY_PLLGMPCTRL = 0x15,
> + PHY_PLLCLKBISTPHASE = 0x17,
> + PHY_TXTERM = 0x19,
> +
> + /* ih_phy_stat0 field values */
> + HDMI_IH_PHY_STAT0_HPD = 0x1,
> +
> + /* ih_mute field values */
> + HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT = 0x2,
> + HDMI_IH_MUTE_MUTE_ALL_INTERRUPT = 0x1,
> +
> + /* tx_invid0 field values */
> + HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE = 0x00,
> + HDMI_TX_INVID0_VIDEO_MAPPING_MASK = 0x1f,
> + HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET = 0,
> +
> + /* tx_instuffing field values */
> + HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE = 0x4,
> + HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE = 0x2,
> + HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE = 0x1,
> +
> + /* vp_pr_cd field values */
> + HDMI_VP_PR_CD_COLOR_DEPTH_MASK = 0xf0,
> + HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET = 4,
> + HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK = 0x0f,
> + HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET = 0,
> +
> + /* vp_stuff field values */
> + HDMI_VP_STUFF_IDEFAULT_PHASE_MASK = 0x20,
> + HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET = 5,
> + HDMI_VP_STUFF_YCC422_STUFFING_MASK = 0x4,
> + HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE = 0x4,
> + HDMI_VP_STUFF_PP_STUFFING_MASK = 0x2,
> + HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE = 0x2,
> + HDMI_VP_STUFF_PR_STUFFING_MASK = 0x1,
> + HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE = 0x1,
> +
> + /* vp_conf field values */
> + HDMI_VP_CONF_BYPASS_EN_MASK = 0x40,
> + HDMI_VP_CONF_BYPASS_EN_ENABLE = 0x40,
> + HDMI_VP_CONF_PP_EN_ENMASK = 0x20,
> + HDMI_VP_CONF_PP_EN_DISABLE = 0x00,
> + HDMI_VP_CONF_PR_EN_MASK = 0x10,
> + HDMI_VP_CONF_PR_EN_DISABLE = 0x00,
> + HDMI_VP_CONF_YCC422_EN_MASK = 0x8,
> + HDMI_VP_CONF_YCC422_EN_DISABLE = 0x0,
> + HDMI_VP_CONF_BYPASS_SELECT_MASK = 0x4,
> + HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER = 0x4,
> + HDMI_VP_CONF_OUTPUT_SELECTOR_MASK = 0x3,
> + HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS = 0x3,
> +
> + /* vp_remap field values */
> + HDMI_VP_REMAP_YCC422_16BIT = 0x0,
> +
> + /* fc_invidconf field values */
> + HDMI_FC_INVIDCONF_HDCP_KEEPOUT_MASK = 0x80,
> + HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE = 0x80,
> + HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE = 0x00,
> + HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_MASK = 0x40,
> + HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH = 0x40,
> + HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW = 0x00,
> + HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_MASK = 0x20,
> + HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH = 0x20,
> + HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW = 0x00,
> + HDMI_FC_INVIDCONF_DE_IN_POLARITY_MASK = 0x10,
> + HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH = 0x10,
> + HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW = 0x00,
> + HDMI_FC_INVIDCONF_DVI_MODEZ_MASK = 0x8,
> + HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE = 0x8,
> + HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE = 0x0,
> + HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_MASK = 0x2,
> + HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH = 0x2,
> + HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW = 0x0,
> + HDMI_FC_INVIDCONF_IN_I_P_MASK = 0x1,
> + HDMI_FC_INVIDCONF_IN_I_P_INTERLACED = 0x1,
> + HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE = 0x0,
> +
> +
> + /* fc_aviconf0-fc_aviconf3 field values */
> + HDMI_FC_AVICONF0_PIX_FMT_MASK = 0x03,
> + HDMI_FC_AVICONF0_PIX_FMT_RGB = 0x00,
> + HDMI_FC_AVICONF0_PIX_FMT_YCBCR422 = 0x01,
> + HDMI_FC_AVICONF0_PIX_FMT_YCBCR444 = 0x02,
> + HDMI_FC_AVICONF0_ACTIVE_FMT_MASK = 0x40,
> + HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT = 0x40,
> + HDMI_FC_AVICONF0_ACTIVE_FMT_NO_INFO = 0x00,
> + HDMI_FC_AVICONF0_BAR_DATA_MASK = 0x0c,
> + HDMI_FC_AVICONF0_BAR_DATA_NO_DATA = 0x00,
> + HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR = 0x04,
> + HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR = 0x08,
> + HDMI_FC_AVICONF0_BAR_DATA_VERT_HORIZ_BAR = 0x0c,
> + HDMI_FC_AVICONF0_SCAN_INFO_MASK = 0x30,
> + HDMI_FC_AVICONF0_SCAN_INFO_OVERSCAN = 0x10,
> + HDMI_FC_AVICONF0_SCAN_INFO_UNDERSCAN = 0x20,
> + HDMI_FC_AVICONF0_SCAN_INFO_NODATA = 0x00,
> +
> + HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_MASK = 0x0f,
> + HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_USE_CODED = 0x08,
> + HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_4_3 = 0x09,
> + HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_16_9 = 0x0a,
> + HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_14_9 = 0x0b,
> + HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_MASK = 0x30,
> + HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_NO_DATA = 0x00,
> + HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_4_3 = 0x10,
> + HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_16_9 = 0x20,
> + HDMI_FC_AVICONF1_COLORIMETRY_MASK = 0xc0,
> + HDMI_FC_AVICONF1_COLORIMETRY_NO_DATA = 0x00,
> + HDMI_FC_AVICONF1_COLORIMETRY_SMPTE = 0x40,
> + HDMI_FC_AVICONF1_COLORIMETRY_ITUR = 0x80,
> + HDMI_FC_AVICONF1_COLORIMETRY_EXTENDED_INFO = 0xc0,
> +
> + HDMI_FC_AVICONF2_SCALING_MASK = 0x03,
> + HDMI_FC_AVICONF2_SCALING_NONE = 0x00,
> + HDMI_FC_AVICONF2_SCALING_HORIZ = 0x01,
> + HDMI_FC_AVICONF2_SCALING_VERT = 0x02,
> + HDMI_FC_AVICONF2_SCALING_HORIZ_vert = 0x03,
> + HDMI_FC_AVICONF2_RGB_QUANT_MASK = 0x0c,
> + HDMI_FC_AVICONF2_RGB_QUANT_DEFAULT = 0x00,
> + HDMI_FC_AVICONF2_RGB_QUANT_LIMITED_RANGE = 0x04,
> + HDMI_FC_AVICONF2_RGB_QUANT_FULL_RANGE = 0x08,
> + HDMI_FC_AVICONF2_EXT_COLORIMETRY_MASK = 0x70,
> + HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601 = 0x00,
> + HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC709 = 0x10,
> + HDMI_FC_AVICONF2_EXT_COLORIMETRY_SYCC601 = 0x20,
> + HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_YCC601 = 0x30,
> + HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_RGB = 0x40,
> + HDMI_FC_AVICONF2_IT_CONTENT_MASK = 0x80,
> + HDMI_FC_AVICONF2_IT_CONTENT_NO_DATA = 0x00,
> + HDMI_FC_AVICONF2_IT_CONTENT_VALID = 0x80,
> +
> + HDMI_FC_AVICONF3_IT_CONTENT_TYPE_MASK = 0x03,
> + HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GRAPHICS = 0x00,
> + HDMI_FC_AVICONF3_IT_CONTENT_TYPE_PHOTO = 0x01,
> + HDMI_FC_AVICONF3_IT_CONTENT_TYPE_CINEMA = 0x02,
> + HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GAME = 0x03,
> + HDMI_FC_AVICONF3_QUANT_RANGE_MASK = 0x0c,
> + HDMI_FC_AVICONF3_QUANT_RANGE_LIMITED = 0x00,
> + HDMI_FC_AVICONF3_QUANT_RANGE_FULL = 0x04,
> +
> + /* fc_gcp field values*/
> + HDMI_FC_GCP_SET_AVMUTE = 0x02,
> + HDMI_FC_GCP_CLEAR_AVMUTE = 0x01,
> +
> + /* phy_conf0 field values */
> + HDMI_PHY_CONF0_PDZ_MASK = 0x80,
> + HDMI_PHY_CONF0_PDZ_OFFSET = 7,
> + HDMI_PHY_CONF0_ENTMDS_MASK = 0x40,
> + HDMI_PHY_CONF0_ENTMDS_OFFSET = 6,
> + HDMI_PHY_CONF0_SPARECTRL_MASK = 0x20,
> + HDMI_PHY_CONF0_SPARECTRL_OFFSET = 5,
> + HDMI_PHY_CONF0_GEN2_PDDQ_MASK = 0x10,
> + HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET = 4,
> + HDMI_PHY_CONF0_GEN2_TXPWRON_MASK = 0x8,
> + HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET = 3,
> + HDMI_PHY_CONF0_SELDATAENPOL_MASK = 0x2,
> + HDMI_PHY_CONF0_SELDATAENPOL_OFFSET = 1,
> + HDMI_PHY_CONF0_SELDIPIF_MASK = 0x1,
> + HDMI_PHY_CONF0_SELDIPIF_OFFSET = 0,
> +
> + /* phy_tst0 field values */
> + HDMI_PHY_TST0_TSTCLR_MASK = 0x20,
> + HDMI_PHY_TST0_TSTCLR_OFFSET = 5,
> +
> + /* phy_stat0 field values */
> + HDMI_PHY_HPD = 0x02,
> + HDMI_PHY_TX_PHY_LOCK = 0x01,
> +
> + /* phy_i2cm_slave_addr field values */
> + HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2 = 0x69,
> +
> + /* phy_i2cm_operation_addr field values */
> + HDMI_PHY_I2CM_OPERATION_ADDR_WRITE = 0x10,
> +
> + /* hdmi_phy_i2cm_int_addr */
> + HDMI_PHY_I2CM_INT_ADDR_DONE_POL = 0x08,
> +
> + /* hdmi_phy_i2cm_ctlint_addr */
> + HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL = 0x80,
> + HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL = 0x08,
> +
> + /* aud_conf0 field values */
> + HDMI_AUD_CONF0_SW_AUDIO_FIFO_RST = 0x80,
> + HDMI_AUD_CONF0_I2S_SELECT = 0x20,
> + HDMI_AUD_CONF0_I2S_IN_EN_0 = 0x01,
> + HDMI_AUD_CONF0_I2S_IN_EN_1 = 0x02,
> + HDMI_AUD_CONF0_I2S_IN_EN_2 = 0x04,
> + HDMI_AUD_CONF0_I2S_IN_EN_3 = 0x08,
> +
> + /* aud_conf0 field values */
> + HDMI_AUD_CONF1_I2S_MODE_STANDARD_MODE = 0x0,
> + HDMI_AUD_CONF1_I2S_WIDTH_16BIT = 0x10,
> +
> + /* aud_n3 field values */
> + HDMI_AUD_N3_NCTS_ATOMIC_WRITE = 0x80,
> + HDMI_AUD_N3_AUDN19_16_MASK = 0x0f,
> +
> + /* aud_cts3 field values */
> + HDMI_AUD_CTS3_N_SHIFT_OFFSET = 5,
> + HDMI_AUD_CTS3_N_SHIFT_MASK = 0xe0,
> + HDMI_AUD_CTS3_N_SHIFT_1 = 0,
> + HDMI_AUD_CTS3_N_SHIFT_16 = 0x20,
> + HDMI_AUD_CTS3_N_SHIFT_32 = 0x40,
> + HDMI_AUD_CTS3_N_SHIFT_64 = 0x60,
> + HDMI_AUD_CTS3_N_SHIFT_128 = 0x80,
> + HDMI_AUD_CTS3_N_SHIFT_256 = 0xa0,
> + HDMI_AUD_CTS3_CTS_MANUAL = 0x10,
> + HDMI_AUD_CTS3_AUDCTS19_16_MASK = 0x0f,
> +
> + /* aud_inputclkfs filed values */
> + HDMI_AUD_INPUTCLKFS_128 = 0x0,
> +
> + /* mc_clkdis field values */
> + HDMI_MC_CLKDIS_AUDCLK_DISABLE = 0x8,
> + HDMI_MC_CLKDIS_TMDSCLK_DISABLE = 0x2,
> + HDMI_MC_CLKDIS_PIXELCLK_DISABLE = 0x1,
> +
> + /* mc_swrstz field values */
> + HDMI_MC_SWRSTZ_II2SSWRST_REQ = 0x08,
> + HDMI_MC_SWRSTZ_TMDSSWRST_REQ = 0x02,
> +
> + /* mc_flowctrl field values */
> + HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH = 0x1,
> + HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS = 0x0,
> +
> + /* mc_phyrstz field values */
> + HDMI_MC_PHYRSTZ_ASSERT = 0x0,
> + HDMI_MC_PHYRSTZ_DEASSERT = 0x1,
> +
> + /* mc_heacphy_rst field values */
> + HDMI_MC_HEACPHY_RST_ASSERT = 0x1,
> +
> + /* i2cm filed values */
> + HDMI_I2CM_SLAVE_DDC_ADDR = 0x50,
> + HDMI_I2CM_SEGADDR_DDC = 0x30,
> + HDMI_I2CM_OP_RD8_EXT = 0x2,
> + HDMI_I2CM_OP_RD8 = 0x1,
> + HDMI_I2CM_DIV_FAST_STD_MODE = 0x8,
> + HDMI_I2CM_DIV_FAST_MODE = 0x8,
> + HDMI_I2CM_DIV_STD_MODE = 0x0,
> + HDMI_I2CM_SOFTRSTZ_MASK = 0x1,
> +};
> +
> +struct hdmi_mpll_config {
> + u64 mpixelclock;
> + /* Mode of Operation and PLL Dividers Control Register */
> + u32 cpce;
> + /* PLL Gmp Control Register */
> + u32 gmp;
> + /* PLL Current Control Register */
> + u32 curr;
> +};
> +
> +struct hdmi_phy_config {
> + u64 mpixelclock;
> + u32 sym_ctr; /* clock symbol and transmitter control */
> + u32 term; /* transmission termination value */
> + u32 vlev_ctr; /* voltage level control */
> +};
> +
> +struct dw_hdmi {
> + ulong ioaddr;
> + const struct hdmi_mpll_config *mpll_cfg;
> + const struct hdmi_phy_config *phy_cfg;
> + u8 i2c_clk_high;
> + u8 i2c_clk_low;
> + u8 reg_io_width;
> +
> + int (*phy_set)(struct dw_hdmi *hdmi, uint mpixelclock);
> +};
> +
> +int dw_hdmi_phy_cfg(struct dw_hdmi *hdmi, uint mpixelclock);
> +int dw_hdmi_phy_wait_for_hpd(struct dw_hdmi *hdmi);
> +void dw_hdmi_phy_init(struct dw_hdmi *hdmi);
> +
> +int dw_hdmi_enable(struct dw_hdmi *hdmi, const struct display_timing *edid);
> +int dw_hdmi_read_edid(struct dw_hdmi *hdmi, u8 *buf, int buf_size);
> +void dw_hdmi_init(struct dw_hdmi *hdmi);
> +
> +#endif
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