[U-Boot] [PATCH 0/8] Allwinner DesignWare DRAM controller refactors and V3s SPL support

[Icenowy Zheng]

Allwinner H5/A64/V3s/R40 SoCs all feature a DRAM controller like the
one in Allwinner H3, which seems from DesignWare.

They do not have properly licensed official DRAM initialization code
(some have even no public readable code), but they can be supported
by slightly altering the H3 code (this can be done by checking
register dump).

This patchset mainly targets on Allwinner V3s support. Allwinner V3s
have a co-packaged 64MiB DDR2 DRAM chip, and a DRAM controller nearly
the same as the one in Allwinner H3 (the chip id of H3 is 0x1680, and
V3s is 0x1681), but with only at most 16-bit bus width. Even the ZQ
quirk in H3 is done in V3s (at least by stock boot0).

Patch 1 makes reusing H3 DRAM code a Kconfig option.

Patch 2 renames bus-width related macros, in order to prepare for
16-bit controllers.

Patch 3 really introduces 16-bit controllers support.

Patch 4 adds bank detection code to H3 DRAM initialization code, as
some DDR2 chips have only 4 banks, not 8.

Patch 5 adds Kconfig options to select DRAM type and timing. This
patch should be merged as soon as possible, as the work to adapt
to Pine64 SoPine/Pinebook and Olimex TERES I needs it (these boards
use A64 and LPDDR3 DRAM).

Patch 6 adds DDR2 support to the DW DRAM code.

Patch 7 adds timing for the DDR2 chip co-packaged with V3s.

Patch 8 really adds support for V3s DRAM controller -- currently
only the DDR2 chip co-packaged with V3s will be used with this
controller. More precise adjustments to the controller is still
TODO, but current code can make it work.

Icenowy Zheng (8):
  sunxi: makes an invisible option for H3-like DRAM controllers
  sunxi: Rename bus-width related macros in H3 DRAM code
  sunxi: add option for 16-bit DW DRAM controller
  sunxi: add bank detection code to H3 DRAM initialization code
  sunxi: Add selective DRAM type and timing
  sunxi: add support for DDR2 DRAM for DesignWare-like DRAM controller
  sunxi: add timing info for the DDR2 in V3s SoC
  sunxi: add support for V3s DRAM controller

 arch/arm/include/asm/arch-sunxi/dram.h             |   4 +-
 .../{dram_sun8i_h3.h => dram_sunxi_dw.h}           |  36 ++++-
 arch/arm/mach-sunxi/Makefile                       |   3 +-
 .../{dram_sun8i_h3.c => dram_sunxi_dw.c}           | 179 +++++++--------------
 arch/arm/mach-sunxi/dram_timings/Makefile          |   2 +
 arch/arm/mach-sunxi/dram_timings/ddr2_v3s.c        |  84 ++++++++++
 arch/arm/mach-sunxi/dram_timings/ddr3_1333.c       |  84 ++++++++++
 board/sunxi/Kconfig                                |  60 +++++++
 8 files changed, 325 insertions(+), 127 deletions(-)
 rename arch/arm/include/asm/arch-sunxi/{dram_sun8i_h3.h => dram_sunxi_dw.h} (85%)
 rename arch/arm/mach-sunxi/{dram_sun8i_h3.c => dram_sunxi_dw.c} (79%)
 create mode 100644 arch/arm/mach-sunxi/dram_timings/Makefile
 create mode 100644 arch/arm/mach-sunxi/dram_timings/ddr2_v3s.c
 create mode 100644 arch/arm/mach-sunxi/dram_timings/ddr3_1333.c

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2.12.0