[U-Boot] [PATCH 0/6] Allwinner DesignWare-like DRAM controllers refactor

[Icenowy Zheng]

Allwinner SoCs after H3 (including H3) seems to use similar DRAM
controllers, which seems to originate from DesignWare.

This patchset did a series of refactors on it, which makes it possible
to support more situations (Allwinner V3s' 16-bit controller and DDR2
DRAM, Pinebook early prototype's dual-rank DDR3, SoPine/Pinebook production
batch's dual-rank LPDDR3). For extra DRAM types (DDR2/LPDDR3) additional
patches are needed, but they are now much easier to write.

This patchset is only part of the original patchset by me which adds V3s
DRAM support. It's taken out because supporting LPDDR3 needs this patchset.
For V3s SPL support I will have another patchset, which depends on the
not-yet-merged V3s support w/o SPL patchset.

Icenowy Zheng (6):
  sunxi: makes an invisible option for H3-like DRAM controllers
  sunxi: Rename bus-width related macros in H3 DRAM code
  sunxi: add option for 16-bit DW DRAM controller
  sunxi: add bank detection code to H3 DRAM initialization code
  sunxi: Add selective DRAM type and timing
  sunxi: enable dual rank detection in DesignWare-like DRAM code

 arch/arm/include/asm/arch-sunxi/dram.h             |   4 +-
 .../{dram_sun8i_h3.h => dram_sunxi_dw.h}           |  36 ++++-
 arch/arm/mach-sunxi/Makefile                       |   3 +-
 .../{dram_sun8i_h3.c => dram_sunxi_dw.c}           | 176 +++++++--------------
 arch/arm/mach-sunxi/dram_timings/Makefile          |   1 +
 arch/arm/mach-sunxi/dram_timings/ddr3_1333.c       |  84 ++++++++++
 board/sunxi/Kconfig                                |  43 +++++
 7 files changed, 219 insertions(+), 128 deletions(-)
 rename arch/arm/include/asm/arch-sunxi/{dram_sun8i_h3.h => dram_sunxi_dw.h} (85%)
 rename arch/arm/mach-sunxi/{dram_sun8i_h3.c => dram_sunxi_dw.c} (79%)
 create mode 100644 arch/arm/mach-sunxi/dram_timings/Makefile
 create mode 100644 arch/arm/mach-sunxi/dram_timings/ddr3_1333.c

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2.12.0