[U-Boot] [PATCH 13/16] dm: x86: board: ivybridge: Add support for CONFIG_BOARD
Simon Glass
sjg at chromium.org
Sun Mar 19 18:59:32 UTC 2017
Add hooks for ivybridge boards so they can use CONFIG_BOARD for init.
Signed-off-by: Simon Glass <sjg at chromium.org>
---
arch/x86/cpu/coreboot/coreboot.c | 2 +
arch/x86/cpu/ivybridge/cpu.c | 71 +++++++++++++++++++----
arch/x86/cpu/ivybridge/sdram.c | 13 ++++-
arch/x86/cpu/ivybridge/sdram_nop.c | 43 +++++++++++++-
arch/x86/cpu/x86_64/cpu.c | 2 +
arch/x86/include/asm/arch-ivybridge/sandybridge.h | 7 +++
arch/x86/lib/spl.c | 13 +++++
board/google/chromebook_link/link.c | 2 +
board/google/chromebox_panther/panther.c | 2 +
9 files changed, 140 insertions(+), 15 deletions(-)
diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c
index 1b042037bb..609bfcb2da 100644
--- a/arch/x86/cpu/coreboot/coreboot.c
+++ b/arch/x86/cpu/coreboot/coreboot.c
@@ -29,6 +29,7 @@ int arch_cpu_init(void)
return x86_cpu_init_f();
}
+#ifndef CONFIG_BOARD_ENABLE
int board_early_init_f(void)
{
return 0;
@@ -38,6 +39,7 @@ int print_cpuinfo(void)
{
return default_print_cpuinfo();
}
+#endif
static void board_final_cleanup(void)
{
diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c
index c4aca08f0d..96e69ef792 100644
--- a/arch/x86/cpu/ivybridge/cpu.c
+++ b/arch/x86/cpu/ivybridge/cpu.c
@@ -12,6 +12,7 @@
*/
#include <common.h>
+#include <board.h>
#include <dm.h>
#include <errno.h>
#include <fdtdec.h>
@@ -50,10 +51,10 @@ int arch_cpu_init(void)
return x86_cpu_init_f();
}
-int arch_cpu_init_dm(void)
+static int do_arch_cpu_init_dm(void)
{
struct pci_controller *hose;
- struct udevice *bus, *dev;
+ struct udevice *bus, *lpc_dev;
int ret;
post_code(0x70);
@@ -67,7 +68,7 @@ int arch_cpu_init_dm(void)
/* TODO(sjg at chromium.org): Get rid of gd->hose */
gd->hose = hose;
- ret = uclass_first_device_err(UCLASS_LPC, &dev);
+ ret = uclass_first_device_err(UCLASS_LPC, &lpc_dev);
if (ret)
return ret;
@@ -83,6 +84,13 @@ int arch_cpu_init_dm(void)
return 0;
}
+#ifndef CONFIG_BOARD_ENABLE
+int arch_cpu_init_dm(void)
+{
+ return do_arch_cpu_init_dm();
+}
+#endif
+
#define PCH_EHCI0_TEMP_BAR0 0xe8000000
#define PCH_EHCI1_TEMP_BAR0 0xe8000400
#define PCH_XHCI_TEMP_BAR0 0xe8001000
@@ -125,12 +133,10 @@ static void enable_usb_bar(struct udevice *bus)
pci_bus_write_config(bus, usb3, PCI_COMMAND, cmd, PCI_SIZE_32);
}
-int print_cpuinfo(void)
+static int ivybridge_checkcpu(void)
{
enum pei_boot_mode_t boot_mode = PEI_BOOT_NONE;
- char processor_name[CPU_MAX_NAME_LEN];
struct udevice *dev, *lpc;
- const char *name;
uint32_t pm1_cnt;
uint16_t pm1_sts;
int ret;
@@ -181,19 +187,62 @@ int print_cpuinfo(void)
}
gd->arch.pei_boot_mode = boot_mode;
-
- /* Print processor name */
- name = cpu_get_name(processor_name);
- printf("CPU: %s\n", name);
-
post_code(POST_CPU_INFO);
return 0;
}
+#ifndef CONFIG_BOARD_ENABLE
+int print_cpuinfo(void)
+{
+ return ivybridge_checkcpu();
+}
+#endif
+
void board_debug_uart_init(void)
{
/* This enables the debug UART */
pci_x86_write_config(NULL, PCH_LPC_DEV, LPC_EN, COMA_LPC_EN,
PCI_SIZE_16);
}
+
+static int cpu_x86_ivybridge_phase(struct udevice *dev,
+ enum board_phase_t phase)
+{
+ switch (phase) {
+ case BOARD_F_ARCH_CPU_INIT_DM:
+ return do_arch_cpu_init_dm();
+ case BOARD_F_CHECKCPU:
+ return ivybridge_checkcpu();
+ case BOARD_F_DRAM_INIT:
+ return ivybridge_dram_init();
+ default:
+ return -ENOSYS;
+ }
+
+ return 0;
+}
+
+static int cpu_x86_ivybridge_board_probe(struct udevice *dev)
+{
+ return board_support_phase_mask(dev,
+ board_phase_mask(BOARD_F_ARCH_CPU_INIT_DM) |
+ board_phase_mask(BOARD_F_CHECKCPU) |
+ board_phase_mask(BOARD_F_DRAM_INIT));
+}
+
+static const struct board_ops cpu_x86_ivybridge_board_ops = {
+ .phase = cpu_x86_ivybridge_phase,
+};
+
+U_BOOT_DRIVER(cpu_x86_ivybridge_board_drv) = {
+ .name = "cpu_x86_ivybridge_board",
+ .id = UCLASS_BOARD,
+ .ops = &cpu_x86_ivybridge_board_ops,
+ .probe = cpu_x86_ivybridge_board_probe,
+ .flags = DM_FLAG_PRE_RELOC,
+};
+
+U_BOOT_DEVICE(cpu_x86_ivybridge_board) = {
+ .name = "cpu_x86_ivybridge_board",
+};
diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c
index 201368c9c7..2484ed4859 100644
--- a/arch/x86/cpu/ivybridge/sdram.c
+++ b/arch/x86/cpu/ivybridge/sdram.c
@@ -401,7 +401,7 @@ static void rcba_config(void)
setbits_le32(RCB_REG(FD), PCH_DISABLE_ALWAYS);
}
-int dram_init(void)
+int ivybridge_dram_init(void)
{
struct pei_data _pei_data __aligned(8) = {
.pei_version = PEI_VERSION,
@@ -541,8 +541,8 @@ int dram_init(void)
/* S3 resume: don't save scrambler seed or MRC data */
if (pei_data->boot_mode != PEI_BOOT_RESUME) {
/*
- * This will be copied to SDRAM in reserve_arch(), then written
- * to SPI flash in mrccache_save()
+ * This will be copied to SDRAM in the BOARD_F_RESERVE_ARCH
+ * call, then written to SPI flash in mrccache_save()
*/
gd->arch.mrc_output = (char *)pei_data->mrc_output;
gd->arch.mrc_output_len = pei_data->mrc_output_len;
@@ -559,3 +559,10 @@ int dram_init(void)
return 0;
}
+
+#ifndef CONFIG_BOARD_ENABLE
+int dram_init(void)
+{
+ return ivybridge_dram_init();
+}
+#endif
diff --git a/arch/x86/cpu/ivybridge/sdram_nop.c b/arch/x86/cpu/ivybridge/sdram_nop.c
index bd1189e447..641d099bbf 100644
--- a/arch/x86/cpu/ivybridge/sdram_nop.c
+++ b/arch/x86/cpu/ivybridge/sdram_nop.c
@@ -5,10 +5,11 @@
*/
#include <common.h>
+#include <asm/arch/sandybridge.h>
DECLARE_GLOBAL_DATA_PTR;
-int dram_init(void)
+int nop_dram_init(void)
{
gd->ram_size = 1ULL << 31;
gd->bd->bi_dram[0].start = 0;
@@ -16,3 +17,43 @@ int dram_init(void)
return 0;
}
+
+#ifndef CONFIG_BOARD_ENABLE
+int dram_init(void)
+{
+ return nop_dram_init();
+}
+#endif
+
+static int cpu_x86_nop_phase(struct udevice *dev, enum board_phase_t phase)
+{
+ switch (phase) {
+ case BOARD_F_DRAM_INIT:
+ return nop_dram_init();
+ default:
+ return -ENOSYS;
+ }
+
+ return 0;
+}
+
+static int cpu_x86_nop_board_probe(struct udevice *dev)
+{
+ return board_support_phase(dev, BOARD_F_DRAM_INIT);
+}
+
+static const struct board_ops cpu_x86_nop_board_ops = {
+ .phase = cpu_x86_nop_phase,
+};
+
+U_BOOT_DRIVER(cpu_x86_nop_board_drv) = {
+ .name = "cpu_x86_nop_board",
+ .id = UCLASS_BOARD,
+ .ops = &cpu_x86_nop_board_ops,
+ .probe = cpu_x86_nop_board_probe,
+ .flags = DM_FLAG_PRE_RELOC,
+};
+
+U_BOOT_DEVICE(cpu_x86_nop_board) = {
+ .name = "cpu_x86_nop_board",
+};
diff --git a/arch/x86/cpu/x86_64/cpu.c b/arch/x86/cpu/x86_64/cpu.c
index db171f750d..ede46f7957 100644
--- a/arch/x86/cpu/x86_64/cpu.c
+++ b/arch/x86/cpu/x86_64/cpu.c
@@ -67,7 +67,9 @@ int misc_init_r(void)
return 0;
}
+#ifndef CONFIG_BOARD_ENABLE
int print_cpuinfo(void)
{
return 0;
}
+#endif
diff --git a/arch/x86/include/asm/arch-ivybridge/sandybridge.h b/arch/x86/include/asm/arch-ivybridge/sandybridge.h
index 8e0f668f0b..52f4c17620 100644
--- a/arch/x86/include/asm/arch-ivybridge/sandybridge.h
+++ b/arch/x86/include/asm/arch-ivybridge/sandybridge.h
@@ -113,4 +113,11 @@
*/
int bridge_silicon_revision(struct udevice *dev);
+/**
+ * ivybridge_dram_init() - Set up SDRAM
+ *
+ * @return 0 if OK, -ve on error
+ */
+int ivybridge_dram_init(void);
+
#endif
diff --git a/arch/x86/lib/spl.c b/arch/x86/lib/spl.c
index fa93d64a7a..a4c1a3ac35 100644
--- a/arch/x86/lib/spl.c
+++ b/arch/x86/lib/spl.c
@@ -48,6 +48,18 @@ static int x86_spl_init(void)
return ret;
}
preloader_console_init();
+#ifdef CONFIG_BOARD_ENABLE
+ ret = board_walk_phase(BOARD_F_CHECKCPU);
+ if (ret) {
+ debug("%s: BOARD_F_CHECKCPU failed\n", __func__);
+ return ret;
+ }
+ ret = board_walk_phase(BOARD_F_DRAM_INIT);
+ if (ret) {
+ debug("%s: BOARD_F_DRAM_INIT failed\n", __func__);
+ return ret;
+ }
+#else
ret = print_cpuinfo();
if (ret) {
debug("%s: print_cpuinfo() failed\n", __func__);
@@ -58,6 +70,7 @@ static int x86_spl_init(void)
debug("%s: dram_init() failed\n", __func__);
return ret;
}
+#endif
memset(&__bss_start, 0, (ulong)&__bss_end - (ulong)&__bss_start);
/* TODO(sjg at chromium.org): Consider calling cpu_init_r() here */
diff --git a/board/google/chromebook_link/link.c b/board/google/chromebook_link/link.c
index 42615e1e23..99b1c91edc 100644
--- a/board/google/chromebook_link/link.c
+++ b/board/google/chromebook_link/link.c
@@ -17,7 +17,9 @@ int arch_early_init_r(void)
return 0;
}
+#ifndef CONFIG_BOARD_ENABLE
int board_early_init_f(void)
{
return 0;
}
+#endif
diff --git a/board/google/chromebox_panther/panther.c b/board/google/chromebox_panther/panther.c
index e3baf88783..151cdd719d 100644
--- a/board/google/chromebox_panther/panther.c
+++ b/board/google/chromebox_panther/panther.c
@@ -12,7 +12,9 @@ int arch_early_init_r(void)
return 0;
}
+#ifndef CONFIG_BOARD_ENABLE
int board_early_init_f(void)
{
return 0;
}
+#endif
--
2.12.0.367.g23dc2f6d3c-goog
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