[U-Boot] [PATCH 15/16] dm: x86: board: ivybridge: Remove old board init code

[Simon Glass]

Remove the legacy board init code since it is no-longer used.

Signed-off-by: Simon Glass <sjg at chromium.org>
---

 arch/x86/cpu/ivybridge/cpu.c             | 16 +---------------
 arch/x86/cpu/ivybridge/sdram.c           |  7 -------
 arch/x86/cpu/ivybridge/sdram_nop.c       |  7 -------
 arch/x86/lib/spl.c                       | 13 -------------
 board/google/chromebook_link/link.c      |  7 -------
 board/google/chromebox_panther/panther.c |  7 -------
 6 files changed, 1 insertion(+), 56 deletions(-)

diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c
index 96e69ef792..e7e6c3168a 100644
--- a/arch/x86/cpu/ivybridge/cpu.c
+++ b/arch/x86/cpu/ivybridge/cpu.c
@@ -84,13 +84,6 @@ static int do_arch_cpu_init_dm(void)
 	return 0;
 }
 
-#ifndef CONFIG_BOARD_ENABLE
-int arch_cpu_init_dm(void)
-{
-	return do_arch_cpu_init_dm();
-}
-#endif
-
 #define PCH_EHCI0_TEMP_BAR0 0xe8000000
 #define PCH_EHCI1_TEMP_BAR0 0xe8000400
 #define PCH_XHCI_TEMP_BAR0  0xe8001000
@@ -133,7 +126,7 @@ static void enable_usb_bar(struct udevice *bus)
 	pci_bus_write_config(bus, usb3, PCI_COMMAND, cmd, PCI_SIZE_32);
 }
 
-static int ivybridge_checkcpu(void)
+int ivybridge_checkcpu(void)
 {
 	enum pei_boot_mode_t boot_mode = PEI_BOOT_NONE;
 	struct udevice *dev, *lpc;
@@ -192,13 +185,6 @@ static int ivybridge_checkcpu(void)
 	return 0;
 }
 
-#ifndef CONFIG_BOARD_ENABLE
-int print_cpuinfo(void)
-{
-	return ivybridge_checkcpu();
-}
-#endif
-
 void board_debug_uart_init(void)
 {
 	/* This enables the debug UART */
diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c
index 2484ed4859..eb4d04f8da 100644
--- a/arch/x86/cpu/ivybridge/sdram.c
+++ b/arch/x86/cpu/ivybridge/sdram.c
@@ -559,10 +559,3 @@ int ivybridge_dram_init(void)
 
 	return 0;
 }
-
-#ifndef CONFIG_BOARD_ENABLE
-int dram_init(void)
-{
-	return ivybridge_dram_init();
-}
-#endif
diff --git a/arch/x86/cpu/ivybridge/sdram_nop.c b/arch/x86/cpu/ivybridge/sdram_nop.c
index 641d099bbf..6bf5366410 100644
--- a/arch/x86/cpu/ivybridge/sdram_nop.c
+++ b/arch/x86/cpu/ivybridge/sdram_nop.c
@@ -18,13 +18,6 @@ int nop_dram_init(void)
 	return 0;
 }
 
-#ifndef CONFIG_BOARD_ENABLE
-int dram_init(void)
-{
-	return nop_dram_init();
-}
-#endif
-
 static int cpu_x86_nop_phase(struct udevice *dev, enum board_phase_t phase)
 {
 	switch (phase) {
diff --git a/arch/x86/lib/spl.c b/arch/x86/lib/spl.c
index a4c1a3ac35..0d40a6f41e 100644
--- a/arch/x86/lib/spl.c
+++ b/arch/x86/lib/spl.c
@@ -48,7 +48,6 @@ static int x86_spl_init(void)
 		return ret;
 	}
 	preloader_console_init();
-#ifdef CONFIG_BOARD_ENABLE
 	ret = board_walk_phase(BOARD_F_CHECKCPU);
 	if (ret) {
 		debug("%s: BOARD_F_CHECKCPU failed\n", __func__);
@@ -59,18 +58,6 @@ static int x86_spl_init(void)
 		debug("%s: BOARD_F_DRAM_INIT failed\n", __func__);
 		return ret;
 	}
-#else
-	ret = print_cpuinfo();
-	if (ret) {
-		debug("%s: print_cpuinfo() failed\n", __func__);
-		return ret;
-	}
-	ret = dram_init();
-	if (ret) {
-		debug("%s: dram_init() failed\n", __func__);
-		return ret;
-	}
-#endif
 	memset(&__bss_start, 0, (ulong)&__bss_end - (ulong)&__bss_start);
 
 	/* TODO(sjg at chromium.org): Consider calling cpu_init_r() here */
diff --git a/board/google/chromebook_link/link.c b/board/google/chromebook_link/link.c
index 99b1c91edc..64e7c1a08d 100644
--- a/board/google/chromebook_link/link.c
+++ b/board/google/chromebook_link/link.c
@@ -16,10 +16,3 @@ int arch_early_init_r(void)
 {
 	return 0;
 }
-
-#ifndef CONFIG_BOARD_ENABLE
-int board_early_init_f(void)
-{
-	return 0;
-}
-#endif
diff --git a/board/google/chromebox_panther/panther.c b/board/google/chromebox_panther/panther.c
index 151cdd719d..ed60e44264 100644
--- a/board/google/chromebox_panther/panther.c
+++ b/board/google/chromebox_panther/panther.c
@@ -11,10 +11,3 @@ int arch_early_init_r(void)
 {
 	return 0;
 }
-
-#ifndef CONFIG_BOARD_ENABLE
-int board_early_init_f(void)
-{
-	return 0;
-}
-#endif
-- 
2.12.0.367.g23dc2f6d3c-goog