[U-Boot] [PATCH v1 34/41] net: mvpp2: Add RX and TX FIFO configuration for PPv2.2

[Joe Hershberger]

On Tue, Mar 21, 2017 at 9:27 AM, Stefan Roese <sr at denx.de> wrote:
> This patch adds the PPv2.2 specific FIFO configuration to the mvpp2
> driver. The RX FIFO packet data size is changed to the recommended
> FIFO sizes. The TX FIFO configuration is newly added.
>
> Signed-off-by: Stefan Roese <sr at denx.de>
> Cc: Stefan Chulski <stefanc at marvell.com>
> Cc: Kostya Porotchkin <kostap at marvell.com>
> Cc: Nadav Haklai <nadavh at marvell.com>
> ---
>
>  drivers/net/mvpp2.c | 75 ++++++++++++++++++++++++++++++++++++++++++++++++-----
>  1 file changed, 68 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
> index 555cd31b19..d5120a8929 100644
> --- a/drivers/net/mvpp2.c
> +++ b/drivers/net/mvpp2.c
> @@ -482,9 +482,23 @@ do {                                                                       \
>  #define MVPP2_TX_DESC_ALIGN            (MVPP2_DESC_ALIGNED_SIZE - 1)
>
>  /* RX FIFO constants */
> -#define MVPP2_RX_FIFO_PORT_DATA_SIZE   0x2000
> -#define MVPP2_RX_FIFO_PORT_ATTR_SIZE   0x80
> -#define MVPP2_RX_FIFO_PORT_MIN_PKT     0x80
> +#define MVPP21_RX_FIFO_PORT_DATA_SIZE          0x2000
> +#define MVPP21_RX_FIFO_PORT_ATTR_SIZE          0x80
> +#define MVPP22_RX_FIFO_10GB_PORT_DATA_SIZE     0x8000
> +#define MVPP22_RX_FIFO_2_5GB_PORT_DATA_SIZE    0x2000
> +#define MVPP22_RX_FIFO_1GB_PORT_DATA_SIZE      0x1000
> +#define MVPP22_RX_FIFO_10GB_PORT_ATTR_SIZE     0x200
> +#define MVPP22_RX_FIFO_2_5GB_PORT_ATTR_SIZE    0x80
> +#define MVPP22_RX_FIFO_1GB_PORT_ATTR_SIZE      0x40
> +#define MVPP2_RX_FIFO_PORT_MIN_PKT             0x80
> +
> +/* TX general registers */
> +#define MVPP22_TX_FIFO_SIZE_REG(eth_tx_port)   (0x8860 + ((eth_tx_port) << 2))
> +#define MVPP22_TX_FIFO_SIZE_MASK               0xf
> +
> +/* TX FIFO constants */
> +#define MVPP2_TX_FIFO_DATA_SIZE_10KB           0xa
> +#define MVPP2_TX_FIFO_DATA_SIZE_3KB            0x3
>
>  /* RX buffer constants */
>  #define MVPP2_SKB_SHINFO_SIZE \
> @@ -3930,10 +3944,35 @@ static void mvpp2_rx_fifo_init(struct mvpp2 *priv)
>         int port;
>
>         for (port = 0; port < MVPP2_MAX_PORTS; port++) {
> -               mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port),
> -                           MVPP2_RX_FIFO_PORT_DATA_SIZE);
> -               mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
> -                           MVPP2_RX_FIFO_PORT_ATTR_SIZE);
> +               if (priv->hw_version == MVPP22) {
> +                       if (port == 0) {
> +                               mvpp2_write(priv,
> +                                           MVPP2_RX_DATA_FIFO_SIZE_REG(port),
> +                                           MVPP22_RX_FIFO_10GB_PORT_DATA_SIZE);
> +                               mvpp2_write(priv,
> +                                           MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
> +                                           MVPP22_RX_FIFO_10GB_PORT_ATTR_SIZE);
> +                       } else if (port == 1) {
> +                               mvpp2_write(priv,
> +                                           MVPP2_RX_DATA_FIFO_SIZE_REG(port),
> +                                           MVPP22_RX_FIFO_2_5GB_PORT_DATA_SIZE);
> +                               mvpp2_write(priv,
> +                                           MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
> +                                           MVPP22_RX_FIFO_2_5GB_PORT_ATTR_SIZE);
> +                       } else {
> +                               mvpp2_write(priv,
> +                                           MVPP2_RX_DATA_FIFO_SIZE_REG(port),
> +                                           MVPP22_RX_FIFO_1GB_PORT_DATA_SIZE);
> +                               mvpp2_write(priv,
> +                                           MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
> +                                           MVPP22_RX_FIFO_1GB_PORT_ATTR_SIZE);
> +                       }
> +               } else {

I would explicitly check for MVPP21 here... The else case should error.

> +                       mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port),
> +                                   MVPP21_RX_FIFO_PORT_DATA_SIZE);
> +                       mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
> +                                   MVPP21_RX_FIFO_PORT_ATTR_SIZE);
> +               }
>         }
>
>         mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG,
> @@ -3941,6 +3980,24 @@ static void mvpp2_rx_fifo_init(struct mvpp2 *priv)
>         mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1);
>  }
>
> +/* Initialize Tx FIFO's */
> +static void mvpp2_tx_fifo_init(struct mvpp2 *priv)
> +{
> +       int port, val;
> +
> +       for (port = 0; port < MVPP2_MAX_PORTS; port++) {
> +               /* Port 0 supports 10KB TX FIFO */
> +               if (port == 0) {
> +                       val = MVPP2_TX_FIFO_DATA_SIZE_10KB &
> +                               MVPP22_TX_FIFO_SIZE_MASK;
> +               } else {
> +                       val = MVPP2_TX_FIFO_DATA_SIZE_3KB &
> +                               MVPP22_TX_FIFO_SIZE_MASK;
> +               }
> +               mvpp2_write(priv, MVPP22_TX_FIFO_SIZE_REG(port), val);
> +       }
> +}
> +
>  static void mvpp2_axi_init(struct mvpp2 *priv)
>  {
>         u32 val, rdval, wrval;
> @@ -4047,6 +4104,10 @@ static int mvpp2_init(struct udevice *dev, struct mvpp2 *priv)
>         /* Rx Fifo Init */
>         mvpp2_rx_fifo_init(priv);
>
> +       /* Tx Fifo Init */
> +       if (priv->hw_version == MVPP22)
> +               mvpp2_tx_fifo_init(priv);
> +
>         /* Reset Rx queue group interrupt configuration */
>         for (i = 0; i < MVPP2_MAX_PORTS; i++) {
>                 if (priv->hw_version == MVPP21)
> --
> 2.12.0
>
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