[U-Boot] [PATCH v2 15/20] arm: socfpga: Add SPL support for Arria 10

[Ley Foon Tan]

On Fri, Mar 10, 2017 at 9:52 AM, Marek Vasut <marex at denx.de> wrote:
> On 03/09/2017 01:26 AM, Ley Foon Tan wrote:
>> Add SPL support for Arria 10 and add reset_uart() to use in SPL.
>>
>> Signed-off-by: Tien Fong Chee <tien.fong.chee at intel.com>
>> Signed-off-by: Ley Foon Tan <ley.foon.tan at intel.com>
>> ---
>>  .../include/mach/reset_manager_arria10.h           |  1 +
>>  arch/arm/mach-socfpga/reset_manager_arria10.c      | 18 +++++++
>>  arch/arm/mach-socfpga/spl.c                        | 55 +++++++++++++++++++++-
>>  3 files changed, 72 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
>> index e3171d1..d0711cf 100644
>> --- a/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
>> +++ b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
>> @@ -14,6 +14,7 @@ void emac_manage_reset(ulong emacbase, uint state);
>>  int reset_deassert_bridges_handoff(void);
>>  void reset_assert_fpga_connected_peripherals(void);
>>  void reset_deassert_osc1wd0(void);
>> +void reset_uart(int assert);
>>
>>  struct socfpga_reset_manager {
>>       u32     stat;
>> diff --git a/arch/arm/mach-socfpga/reset_manager_arria10.c b/arch/arm/mach-socfpga/reset_manager_arria10.c
>> index 547a8bb..bbf54f0 100644
>> --- a/arch/arm/mach-socfpga/reset_manager_arria10.c
>> +++ b/arch/arm/mach-socfpga/reset_manager_arria10.c
>> @@ -28,6 +28,24 @@ static const struct socfpga_system_manager *sysmgr_regs =
>>       ALT_RSTMGR_PER0MODRST_QSPIECC_SET_MSK | \
>>       ALT_RSTMGR_PER0MODRST_SDMMCECC_SET_MSK)
>
> Should be part of reset manager patch ...
Do you mean by the reset_uart() below? In the last review, you comment
that uart_com_port() is in later patch (misc path) of reset manager
patch. So, I moved this function to this here. Let me know if you
prefer a new patch this reset_uart().

>
>> +void reset_uart(int assert)
>> +{
>> +     u32 mask = 0;
>> +     unsigned int com_port;
>> +
>> +     com_port = uart_com_port(gd->fdt_blob);
>> +
>> +     if (com_port == SOCFPGA_UART1_ADDRESS)
>> +             mask |= ALT_RSTMGR_PER1MODRST_UART1_SET_MSK;
>> +     else if (com_port == SOCFPGA_UART0_ADDRESS)
>> +             mask |= ALT_RSTMGR_PER1MODRST_UART0_SET_MSK;
>> +
>> +     if (assert)
>> +             setbits_le32(&reset_manager_base->per1modrst, mask);
>> +     else
>> +             clrbits_le32(&reset_manager_base->per1modrst, mask);
>> +}
>> +
>>  static const u32 per0fpgamasks[] = {
>>       ALT_RSTMGR_PER0MODRST_EMACECC0_SET_MSK |
>>       ALT_RSTMGR_PER0MODRST_EMAC0_SET_MSK,
>> diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-socfpga/spl.c
>> index fec4c7a..5c0cc98 100644
>> --- a/arch/arm/mach-socfpga/spl.c
>> +++ b/arch/arm/mach-socfpga/spl.c
>> @@ -19,23 +19,32 @@
>>  #include <asm/arch/sdram.h>
>>  #include <asm/arch/scu.h>
>>  #include <asm/arch/nic301.h>
>> +#include <asm/sections.h>
>> +#include <fdtdec.h>
>> +#include <watchdog.h>
>> +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
>> +#include <asm/arch/pinmux.h>
>> +#endif
>>
>>  DECLARE_GLOBAL_DATA_PTR;
>>
>> +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
>>  static struct pl310_regs *const pl310 =
>>       (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
>>  static struct scu_registers *scu_regs =
>>       (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
>>  static struct nic301_registers *nic301_regs =
>>       (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
>> -static struct socfpga_system_manager *sysmgr_regs =
>> +#endif
>> +
>> +static const struct socfpga_system_manager *sysmgr_regs =
>>       (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
>>
>>  u32 spl_boot_device(void)
>>  {
>>       const u32 bsel = readl(&sysmgr_regs->bootinfo);
>>
>> -     switch (bsel & 0x7) {
>> +     switch ((bsel >> SYSMGR_BOOTINFO_BSEL_SHIFT) & 0x7) {
>>       case 0x1:       /* FPGA (HPS2FPGA Bridge) */
>>               return BOOT_DEVICE_RAM;
>>       case 0x2:       /* NAND Flash (1.8V) */
>> @@ -68,6 +77,7 @@ u32 spl_boot_mode(const u32 boot_device)
>>  }
>>  #endif
>>
>> +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
>>  static void socfpga_nic301_slave_ns(void)
>>  {
>>       writel(0x1, &nic301_regs->lwhps2fpgaregs);
>> @@ -182,3 +192,44 @@ void board_init_f(ulong dummy)
>>       /* Configure simple malloc base pointer into RAM. */
>>       gd->malloc_base = CONFIG_SYS_TEXT_BASE + (1024 * 1024);
>>  }
>> +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
>> +#ifdef CONFIG_SPL_BOARD_INIT
>> +void spl_board_init(void)
>> +{
>> +     /* configuring the clock based on handoff */
>> +     cm_basic_init(gd->fdt_blob);
>> +     WATCHDOG_RESET();
>> +
>> +     config_dedicated_pins(gd->fdt_blob);
>> +     WATCHDOG_RESET();
>> +
>> +     /* Release UART from reset */
>> +     reset_uart(0);
>> +
>> +     /* enable console uart printing */
>> +     preloader_console_init();
>> +}
>> +#endif
>> +
>> +void board_init_f(ulong dummy)
>> +{
>> +     /*
>> +      * Configure Clock Manager to use intosc clock instead external osc to
>> +      * ensure success watchdog operation. We do it as early as possible.
>> +      */
>> +     cm_use_intosc();
>> +
>> +     watchdog_disable();
>> +
>> +     arch_early_init_r();
>> +
>> +#ifdef CONFIG_HW_WATCHDOG
>> +     /* release osc1 watchdog timer 0 from reset */
>> +     reset_deassert_osc1wd0();
>> +
>> +     /* reconfigure and enable the watchdog */
>> +     hw_watchdog_init();
>> +     WATCHDOG_RESET();
>> +#endif /* CONFIG_HW_WATCHDOG */
>> +}
>> +#endif

Regards
Ley Foon