[U-Boot] [PATCH 1/6] rockchip: pinctrl: rk3399: add GMAC (RGMII only) support
Philipp Tomsich
philipp.tomsich at theobroma-systems.com
Fri Mar 24 18:24:23 UTC 2017
To add GMAC (Gigabit Ethernet) support (limited to RGMII only at this
point), we need support for additional pin-configuration. This commit
adds the pinctrl support for GMAC in RGMII signalling mode:
* adds a PERIPH_ID_GMAC and the mapping from IRQ number to PERIPH_ID
* adds the required defines (in the GRF support) for configuring the
GPIOC pins for RGMII
* configures the RGMII pins (in GPIOC) when requested via pinctrl
X-AffectedPlatforms: RK3399-Q7
Signed-off-by: Philipp Tomsich <philipp.tomsich at theobroma-systems.com>
---
arch/arm/include/asm/arch-rockchip/grf_rk3399.h | 37 ++++++++++++++++++++++
arch/arm/include/asm/arch-rockchip/periph.h | 1 +
drivers/pinctrl/rockchip/pinctrl_rk3399.c | 42 +++++++++++++++++++++++++
3 files changed, 80 insertions(+)
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h
index 4701cfb..8e20533 100644
--- a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h
@@ -342,23 +342,60 @@ enum {
GRF_UART0BT_SOUT = 1,
/* GRF_GPIO3A_IOMUX */
+ GRF_GPIO3A0_SEL_SHIFT = 0,
+ GRF_GPIO3A0_SEL_MASK = 3 << GRF_GPIO3A0_SEL_SHIFT,
+ GRF_MAC_TXD2 = 1,
+ GRF_GPIO3A1_SEL_SHIFT = 2,
+ GRF_GPIO3A1_SEL_MASK = 3 << GRF_GPIO3A1_SEL_SHIFT,
+ GRF_MAC_TXD3 = 1,
+ GRF_GPIO3A2_SEL_SHIFT = 4,
+ GRF_GPIO3A2_SEL_MASK = 3 << GRF_GPIO3A2_SEL_SHIFT,
+ GRF_MAC_RXD2 = 1,
+ GRF_GPIO3A3_SEL_SHIFT = 6,
+ GRF_GPIO3A3_SEL_MASK = 3 << GRF_GPIO3A3_SEL_SHIFT,
+ GRF_MAC_RXD3 = 1,
GRF_GPIO3A4_SEL_SHIFT = 8,
GRF_GPIO3A4_SEL_MASK = 3 << GRF_GPIO3A4_SEL_SHIFT,
+ GRF_MAC_TXD0 = 1,
GRF_SPI0NORCODEC_RXD = 2,
GRF_GPIO3A5_SEL_SHIFT = 10,
GRF_GPIO3A5_SEL_MASK = 3 << GRF_GPIO3A5_SEL_SHIFT,
+ GRF_MAC_TXD1 = 1,
GRF_SPI0NORCODEC_TXD = 2,
GRF_GPIO3A6_SEL_SHIFT = 12,
GRF_GPIO3A6_SEL_MASK = 3 << GRF_GPIO3A6_SEL_SHIFT,
+ GRF_MAC_RXD0 = 1,
GRF_SPI0NORCODEC_CLK = 2,
GRF_GPIO3A7_SEL_SHIFT = 14,
GRF_GPIO3A7_SEL_MASK = 3 << GRF_GPIO3A7_SEL_SHIFT,
+ GRF_MAC_RXD1 = 1,
GRF_SPI0NORCODEC_CSN0 = 2,
/* GRF_GPIO3B_IOMUX */
GRF_GPIO3B0_SEL_SHIFT = 0,
GRF_GPIO3B0_SEL_MASK = 3 << GRF_GPIO3B0_SEL_SHIFT,
+ GRF_MAC_MDC = 1,
GRF_SPI0NORCODEC_CSN1 = 2,
+ GRF_GPIO3B1_SEL_SHIFT = 2,
+ GRF_GPIO3B1_SEL_MASK = 3 << GRF_GPIO3B1_SEL_SHIFT,
+ GRF_MAC_RXDV = 1,
+ GRF_GPIO3B3_SEL_SHIFT = 6,
+ GRF_GPIO3B3_SEL_MASK = 3 << GRF_GPIO3B3_SEL_SHIFT,
+ GRF_MAC_CLK = 1,
+ GRF_GPIO3B4_SEL_SHIFT = 8,
+ GRF_GPIO3B4_SEL_MASK = 3 << GRF_GPIO3B4_SEL_SHIFT,
+ GRF_MAC_TXEN = 1,
+ GRF_GPIO3B5_SEL_SHIFT = 10,
+ GRF_GPIO3B5_SEL_MASK = 3 << GRF_GPIO3B5_SEL_SHIFT,
+ GRF_MAC_MDIO = 1,
+ GRF_GPIO3B6_SEL_SHIFT = 12,
+ GRF_GPIO3B6_SEL_MASK = 3 << GRF_GPIO3B6_SEL_SHIFT,
+ GRF_MAC_RXCLK = 1,
+
+ /* GRF_GPIO3C_IOMUX */
+ GRF_GPIO3C1_SEL_SHIFT = 2,
+ GRF_GPIO3C1_SEL_MASK = 3 << GRF_GPIO3C1_SEL_SHIFT,
+ GRF_MAC_TXCLK = 1,
/* GRF_GPIO4B_IOMUX */
GRF_GPIO4B0_SEL_SHIFT = 0,
diff --git a/arch/arm/include/asm/arch-rockchip/periph.h b/arch/arm/include/asm/arch-rockchip/periph.h
index fa6069b..239a274 100644
--- a/arch/arm/include/asm/arch-rockchip/periph.h
+++ b/arch/arm/include/asm/arch-rockchip/periph.h
@@ -38,6 +38,7 @@ enum periph_id {
PERIPH_ID_SDMMC1,
PERIPH_ID_SDMMC2,
PERIPH_ID_HDMI,
+ PERIPH_ID_GMAC,
PERIPH_ID_COUNT,
diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3399.c b/drivers/pinctrl/rockchip/pinctrl_rk3399.c
index a74793a..507bec4 100644
--- a/drivers/pinctrl/rockchip/pinctrl_rk3399.c
+++ b/drivers/pinctrl/rockchip/pinctrl_rk3399.c
@@ -202,6 +202,39 @@ static void pinctrl_rk3399_sdmmc_config(struct rk3399_grf_regs *grf, int mmc_id)
}
}
+#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
+static void pinctrl_rk3399_gmac_config(struct rk3399_grf_regs *grf, int mmc_id)
+{
+ rk_clrsetreg(&grf->gpio3a_iomux,
+ GRF_GPIO3A0_SEL_MASK | GRF_GPIO3A1_SEL_MASK |
+ GRF_GPIO3A2_SEL_MASK | GRF_GPIO3A3_SEL_MASK |
+ GRF_GPIO3A4_SEL_MASK | GRF_GPIO3A5_SEL_MASK |
+ GRF_GPIO3A6_SEL_MASK | GRF_GPIO3A7_SEL_MASK,
+ GRF_MAC_TXD2 << GRF_GPIO3A0_SEL_SHIFT |
+ GRF_MAC_TXD3 << GRF_GPIO3A1_SEL_SHIFT |
+ GRF_MAC_RXD2 << GRF_GPIO3A2_SEL_SHIFT |
+ GRF_MAC_RXD3 << GRF_GPIO3A3_SEL_SHIFT |
+ GRF_MAC_TXD0 << GRF_GPIO3A4_SEL_SHIFT |
+ GRF_MAC_TXD1 << GRF_GPIO3A5_SEL_SHIFT |
+ GRF_MAC_RXD0 << GRF_GPIO3A6_SEL_SHIFT |
+ GRF_MAC_RXD1 << GRF_GPIO3A7_SEL_SHIFT);
+ rk_clrsetreg(&grf->gpio3b_iomux,
+ GRF_GPIO3B0_SEL_MASK | GRF_GPIO3B1_SEL_MASK |
+ GRF_GPIO3B3_SEL_MASK |
+ GRF_GPIO3B4_SEL_MASK | GRF_GPIO3B5_SEL_MASK |
+ GRF_GPIO3B6_SEL_MASK,
+ GRF_MAC_MDC << GRF_GPIO3B0_SEL_SHIFT |
+ GRF_MAC_RXDV << GRF_GPIO3B1_SEL_SHIFT |
+ GRF_MAC_CLK << GRF_GPIO3B3_SEL_SHIFT |
+ GRF_MAC_TXEN << GRF_GPIO3B4_SEL_SHIFT |
+ GRF_MAC_MDIO << GRF_GPIO3B5_SEL_SHIFT |
+ GRF_MAC_RXCLK << GRF_GPIO3B6_SEL_SHIFT);
+ rk_clrsetreg(&grf->gpio3c_iomux,
+ GRF_GPIO3C1_SEL_MASK,
+ GRF_MAC_TXCLK << GRF_GPIO3C1_SEL_SHIFT);
+}
+#endif
+
static int rk3399_pinctrl_request(struct udevice *dev, int func, int flags)
{
struct rk3399_pinctrl_priv *priv = dev_get_priv(dev);
@@ -243,6 +276,11 @@ static int rk3399_pinctrl_request(struct udevice *dev, int func, int flags)
case PERIPH_ID_SDMMC1:
pinctrl_rk3399_sdmmc_config(priv->grf, func);
break;
+#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
+ case PERIPH_ID_GMAC:
+ pinctrl_rk3399_gmac_config(priv->grf, func);
+ break;
+#endif
default:
return -EINVAL;
}
@@ -283,6 +321,10 @@ static int rk3399_pinctrl_get_periph_id(struct udevice *dev,
return PERIPH_ID_I2C5;
case 65:
return PERIPH_ID_SDMMC1;
+#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
+ case 12:
+ return PERIPH_ID_GMAC;
+#endif
}
#endif
return -ENOENT;
--
1.9.1
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