[U-Boot] [PATCH 07/17] board_f: Remove adjust_sdram_tbs_8xx() from the init sequence

[Simon Glass]

We can just call this from the only place that needs it.

Signed-off-by: Simon Glass <sjg at chromium.org>
---

 arch/powerpc/cpu/mpc8xx/speed.c | 63 +++++++++++++++++++++--------------------
 common/board_f.c                |  4 ---
 include/common.h                |  1 -
 3 files changed, 33 insertions(+), 35 deletions(-)

diff --git a/arch/powerpc/cpu/mpc8xx/speed.c b/arch/powerpc/cpu/mpc8xx/speed.c
index 7a532cca07..e2295d253f 100644
--- a/arch/powerpc/cpu/mpc8xx/speed.c
+++ b/arch/powerpc/cpu/mpc8xx/speed.c
@@ -252,6 +252,33 @@ static int sdram_adjust_866(void)
 	return 0;
 }
 
+/*
+ * Adjust sdram refresh rate to actual CPU clock
+ * and set timebase source according to actual CPU clock
+ */
+static int adjust_sdram_tbs_8xx(void)
+{
+#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) && \
+		!defined(CONFIG_TQM885D)
+	volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+	long		  mamr;
+	long              sccr;
+
+	mamr = immr->im_memctl.memc_mamr;
+	mamr &= ~MAMR_PTA_MSK;
+	mamr |= ((gd->cpu_clk / CONFIG_SYS_PTA_PER_CLK) << MAMR_PTA_SHIFT);
+	immr->im_memctl.memc_mamr = mamr;
+
+	if (gd->cpu_clk < 67000000) {
+		sccr = immr->im_clkrst.car_sccr;
+		sccr |= SCCR_TBS;
+		immr->im_clkrst.car_sccr = sccr;
+	}
+#endif /* CONFIG_TQM8xxL/M, !TQM866M, !TQM885D */
+
+	return 0;
+}
+
 /* This function sets up PLL (init_pll_866() is called) and
  * fills gd->cpu_clk and gd->bus_clk according to the environment
  * variable 'cpuclk' or to CONFIG_8xx_CPUCLK_DEFAULT (if 'cpuclk'
@@ -264,6 +291,7 @@ int get_clocks(void)
 	char		  tmp[64];
 	long		  cpuclk = 0;
 	long		  sccr_reg;
+	int ret;
 
 	if (getenv_f("cpuclk", tmp, sizeof (tmp)) > 0)
 		cpuclk = simple_strtoul (tmp, NULL, 10) * 1000000;
@@ -293,7 +321,11 @@ int get_clocks(void)
 	}
 	immr->im_clkrst.car_sccr = sccr_reg;
 
-	return sdram_adjust_866();
+	ret = sdram_adjust_866();
+	if (ret)
+		return ret;
+
+	return adjust_sdram_tbs_8xx();
 }
 
 /* Configure PLL for MPC866/859/885 CPU series
@@ -369,32 +401,3 @@ static long init_pll_866 (long clk)
 }
 
 #endif /* CONFIG_8xx_CPUCLK_DEFAULT */
-
-#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) \
-    && !defined(CONFIG_TQM885D)
-/*
- * Adjust sdram refresh rate to actual CPU clock
- * and set timebase source according to actual CPU clock
- */
-int adjust_sdram_tbs_8xx (void)
-{
-	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
-	long		  mamr;
-	long              sccr;
-
-	mamr = immr->im_memctl.memc_mamr;
-	mamr &= ~MAMR_PTA_MSK;
-	mamr |= ((gd->cpu_clk / CONFIG_SYS_PTA_PER_CLK) << MAMR_PTA_SHIFT);
-	immr->im_memctl.memc_mamr = mamr;
-
-	if (gd->cpu_clk < 67000000) {
-		sccr = immr->im_clkrst.car_sccr;
-		sccr |= SCCR_TBS;
-		immr->im_clkrst.car_sccr = sccr;
-	}
-
-	return (0);
-}
-#endif /* CONFIG_TQM8xxL/M, !TQM866M, !TQM885D */
-
-/* ------------------------------------------------------------------------- */
diff --git a/common/board_f.c b/common/board_f.c
index 14035b1805..7feffa4939 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -850,10 +850,6 @@ static const init_fnc_t init_sequence_f[] = {
 	init_timebase,
 #elif defined(CONFIG_PPC)
 	get_clocks,		/* get CPU and bus clocks (etc.) */
-#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) \
-		&& !defined(CONFIG_TQM885D)
-	adjust_sdram_tbs_8xx,
-#endif
 	/* TODO: can we rename this to timer_init()? */
 	init_timebase,
 #endif /* CONFIG_8xx_CPUCLK_DEFAULT */
diff --git a/include/common.h b/include/common.h
index ef12e44095..ce37e9fc59 100644
--- a/include/common.h
+++ b/include/common.h
@@ -640,7 +640,6 @@ int serial_stub_tstc(struct stdio_dev *sdev);
 
 /* $(CPU)/speed.c */
 int	get_clocks (void);
-int	adjust_sdram_tbs_8xx (void);
 #if defined(CONFIG_MPC8260)
 int	prt_8260_clks (void);
 #elif defined(CONFIG_MPC5xxx)
-- 
2.12.2.564.g063fe858b8-goog