[U-Boot] [PATCH v3 15/19] drivers: fpga: Add compile switch for Gen5 only registers

[Ley Foon Tan]

These registers only available for Gen5 device, exclude them
from Arria 10 build.

Signed-off-by: Tien Fong Chee <tien.fong.chee at intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan at intel.com>
---
 drivers/fpga/socfpga.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/fpga/socfpga.c b/drivers/fpga/socfpga.c
index f1b2f2c..3751574 100644
--- a/drivers/fpga/socfpga.c
+++ b/drivers/fpga/socfpga.c
@@ -19,8 +19,10 @@ DECLARE_GLOBAL_DATA_PTR;
 
 static struct socfpga_fpga_manager *fpgamgr_regs =
 	(struct socfpga_fpga_manager *)SOCFPGA_FPGAMGRREGS_ADDRESS;
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 static struct socfpga_system_manager *sysmgr_regs =
 	(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
+#endif
 
 /* Set CD ratio */
 static void fpgamgr_set_cd_ratio(unsigned long ratio)
@@ -268,8 +270,10 @@ int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
 
 	/* Prior programming the FPGA, all bridges need to be shut off */
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 	/* Disable all signals from hps peripheral controller to fpga */
 	writel(0, &sysmgr_regs->fpgaintfgrp_module);
+#endif
 
 	/* Disable all signals from FPGA to HPS SDRAM */
 #define SDR_CTRLGRP_FPGAPORTRST_ADDRESS	0x5080
@@ -278,8 +282,10 @@ int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
 	/* Disable all axi bridge (hps2fpga, lwhps2fpga & fpga2hps) */
 	socfpga_bridges_reset(1);
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 	/* Unmap the bridges from NIC-301 */
 	writel(0x1, SOCFPGA_L3REGS_ADDRESS);
+#endif
 
 	/* Initialize the FPGA Manager */
 	status = fpgamgr_program_init();
-- 
2.2.0