[U-Boot] [PATCH v4 09/11] sun5/7i: add an implementation of the psci suspend function

[Antoine Tenart]

Hi Maxime,

On Mon, May 01, 2017 at 11:13:27PM +0200, Maxime Ripard wrote:
> On Sun, Apr 30, 2017 at 03:29:54PM +0200, Antoine Tenart wrote:
> > +
> > +static void __secure sunxi_clock_enter_idle(struct sunxi_ccm_reg *ccm)
> > +{
> > +	/* switch cpuclk to osc24m */
> > +	clrsetbits_le32(&ccm->cpu_ahb_apb0_cfg, 0x3 << CPU_CLK_SRC_SHIFT,
> > +			CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT);
> > +
> > +	/* disable pll1 */
> > +	clrbits_le32(&ccm->pll1_cfg, CCM_PLL1_CTRL_EN);
> > +
> > +#ifndef CONFIG_MACH_SUN7I
> > +	/*
> > +	 * Switch cpuclk to losc. Based on my experience this didn't worked for
> > +	 * sun7i, hence the ifndef.
> > +	 */
> > +	clrbits_le32(&ccm->cpu_ahb_apb0_cfg, 0x3 << CPU_CLK_SRC_SHIFT);
> > +#endif
> 
> Do we enter idle per-core, or is it a cluster-wide state?

This is cluster-wise, as sunxi_clock_enter_idle() is only called when
all CPU are in IDLE state (called the PSCI suspend function). See
psci_cpu_suspend().

> The A20 has a single clock for both CPUs, so that might explain why it
> didn't work for you: if you enter idle for only one core, and change
> the clock for both, then you're probably crashing the second core in
> the process.
> 
> > +static void __secure sunxi_clock_leave_idle(struct sunxi_ccm_reg *ccm)
> > +{
> > +#ifndef CONFIG_MACH_SUN7I
> > +	/* switch cpuclk to osc24m */
> > +	clrsetbits_le32(&ccm->cpu_ahb_apb0_cfg, 0x3 << CPU_CLK_SRC_SHIFT,
> > +			CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT);
> > +#endif
> 
> Is that really needed? Whatever state we're in at this point, we just
> want to switch back to the PLL1, right?

I think it wasn't working for some reasons if we didn't switch to osc24m
first, but that was a while ago. I can test again.

Thanks,
Antoine

-- 
Antoine Ténart, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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