[U-Boot] [PATCH] pico-imx7d: Add initial support
Stefano Babic
sbabic at denx.de
Tue May 9 08:23:59 UTC 2017
Hi Jagan, Vanessa,
On 08/05/2017 21:49, Jagan Teki wrote:
> Though the code look good and similar approach of existing boards, I'm
> little concern of continue the same legacy and w/o trying new feature
> like fdt.
>
> We've few i.MX boards which uses fdt support please refer the same.
> I'm commenting below what all the code can removed ans use it with
> dts.
It is worth a couple og thoughts. Even if the path to a u-boot
configured via fdt is clear, this should be done if this does not block
other feature that are maybe important for the project - and this is
known only by the board maintainer. I do not talk about this particular
board - the issue is general and I remain general.
For example, it looks to me that having a single binary for multiple
variants of the board cannot be easy reached. There is a DTS for each
variant and this means a binary for each of them. This is ok for some
projects, it is not ok for some other ones. And I cannot constrain
people to go into a direction when they lose features.
I did quite the same approach with SPL / u-boot.imx. I understand that
some projects want to stick with a single binary instead of two, it
remains a decision of board maintainer. No block on my site.
Last concern is related to size in SPL. imx6.Solo has just 64Kb RAM, but
less are available because a part is reserved to the BootRom (or HAB, or
whatever). And putting a lot of stuff inside SPL is not possible, then.
After saying all this, back to the specific case. Vanessa, you are not
using SPL and you have put the RAM configuration into the DCD table.
Then it is everything fix and you cannot have more variants. That means
your board has not the drawbacks I mentioned above. It could be a good
candidate to use dts. What do you think ?
Best regards,
Stefano Babic
>
>>
>> diff --git a/arch/arm/cpu/armv7/mx7/Kconfig b/arch/arm/cpu/armv7/mx7/Kconfig
>> index 8dfb4c9..366fd34 100644
>> --- a/arch/arm/cpu/armv7/mx7/Kconfig
>> +++ b/arch/arm/cpu/armv7/mx7/Kconfig
>> @@ -23,6 +23,13 @@ config TARGET_MX7DSABRESD
>> select DM
>> select DM_THERMAL
>>
>> +config TARGET_PICO_IMX7D
>> + bool "pico-imx7d"
>> + select BOARD_LATE_INIT
>> + select MX7D
>> + select DM
>> + select DM_THERMAL
>> +
>> config TARGET_WARP7
>> bool "warp7"
>> select BOARD_LATE_INIT
>> @@ -43,6 +50,7 @@ config SYS_SOC
>> default "mx7"
>>
>> source "board/freescale/mx7dsabresd/Kconfig"
>> +source "board/technexion/pico-imx7d/Kconfig"
>> source "board/toradex/colibri_imx7/Kconfig"
>> source "board/warp7/Kconfig"
>>
>> diff --git a/board/technexion/pico-imx7d/Kconfig b/board/technexion/pico-imx7d/Kconfig
>> new file mode 100644
>> index 0000000..f4ae18c
>> --- /dev/null
>> +++ b/board/technexion/pico-imx7d/Kconfig
>> @@ -0,0 +1,15 @@
>> +if TARGET_PICO_IMX7D
>> +
>> +config SYS_BOARD
>> + default "pico-imx7d"
>> +
>> +config SYS_VENDOR
>> + default "technexion"
>> +
>> +config SYS_SOC
>> + default "mx7"
>> +
>> +config SYS_CONFIG_NAME
>> + default "pico-imx7d"
>> +
>> +endif
>> diff --git a/board/technexion/pico-imx7d/MAINTAINERS b/board/technexion/pico-imx7d/MAINTAINERS
>> new file mode 100644
>> index 0000000..276162a
>> --- /dev/null
>> +++ b/board/technexion/pico-imx7d/MAINTAINERS
>> @@ -0,0 +1,7 @@
>> +Technexion PICO-IMX7D board
>> +M: Wig Cheng <wig.cheng at technexion.com>
>> +M: Vanessa Maegima <vanessa.maegima at nxp.com>
>> +S: Maintained
>> +F: board/technexion/pico-imx7d/
>> +F: include/configs/pico-imx7d.h
>> +F: configs/pico-imx7d_defconfig
>> diff --git a/board/technexion/pico-imx7d/Makefile b/board/technexion/pico-imx7d/Makefile
>> new file mode 100644
>> index 0000000..42cca47
>> --- /dev/null
>> +++ b/board/technexion/pico-imx7d/Makefile
>> @@ -0,0 +1,6 @@
>> +# (C) Copyright 2017 NXP Semiconductors
>> +#
>> +# SPDX-License-Identifier: GPL-2.0+
>> +#
>> +
>> +obj-y := pico-imx7d.o
>> diff --git a/board/technexion/pico-imx7d/README b/board/technexion/pico-imx7d/README
>> new file mode 100644
>> index 0000000..a2805ee
>> --- /dev/null
>> +++ b/board/technexion/pico-imx7d/README
>> @@ -0,0 +1,49 @@
>> +How to update U-Boot on pico-imx7d board
>> +----------------------------------------
>> +
>> +Required software on the host PC:
>> +
>> +- imx_usb_loader: https://github.com/boundarydevices/imx_usb_loader
>> +
>> +Build U-Boot for pico:
>> +
>> +$ make mrproper
>> +$ make pico-imx7d_defconfig
>> +$ make
>> +
>> +This generates the U-Boot binary called u-boot.imx.
>> +
>> +Put pico board in USB download mode (refer to the PICO-iMX7D Quick Start Guide
>> +page 3)
>> +
>> +Connect a USB to serial adapter between the host PC and pico.
>> +
>> +Connect a USB cable between the OTG pico port and the host PC.
>> +
>> +Open a terminal program such as minicom.
>> +
>> +Copy u-boot.imx to the imx_usb_loader folder.
>> +
>> +Load u-boot.imx via USB:
>> +
>> +$ sudo ./imx_usb u-boot.imx
>> +
>> +Then U-Boot starts and its messages appear in the console program.
>> +
>> +Use the default environment variables:
>> +
>> +=> env default -f -a
>> +=> saveenv
>> +
>> +Run the UMS command:
>> +=> ums 0 mmc 0
>> +
>> +Transfer u-boot.imx to be flashed into the eMMC:
>> +
>> +$ sudo dd if=u-boot.imx of=/dev/sdX bs=1K seek=1; sync
>> +
>> +Remove power from the pico board.
>> +
>> +Put pico board into normal boot mode.
>> +
>> +Power up the board and the new updated U-Boot should boot from eMMC.
>> diff --git a/board/technexion/pico-imx7d/imximage.cfg b/board/technexion/pico-imx7d/imximage.cfg
>> new file mode 100644
>> index 0000000..202956a
>> --- /dev/null
>> +++ b/board/technexion/pico-imx7d/imximage.cfg
>> @@ -0,0 +1,98 @@
>> +/*
>> + * Copyright (C) 2017 Freescale Semiconductor, Inc.
>> + *
>> + * SPDX-License-Identifier: GPL-2.0+
>> + *
>> + * Refer docs/README.imxmage for more details about how-to configure
>> + * and create imximage boot image
>> + *
>> + * The syntax is taken as close as possible with the kwbimage
>> + */
>> +
>> +#define __ASSEMBLY__
>> +#include <config.h>
>> +
>> +/* image version */
>> +
>> +IMAGE_VERSION 2
>> +
>> +BOOT_FROM sd
>> +
>> +/* Secure boot support */
>> +#ifdef CONFIG_SECURE_BOOT
>> +CSF CONFIG_CSF_SIZE
>> +#endif
>> +
>> +/*
>> + * Device Configuration Data (DCD)
>> + *
>> + * Each entry must have the format:
>> + * Addr-type Address Value
>> + *
>> + * where:
>> + * Addr-type register length (1,2 or 4 bytes)
>> + * Address absolute address of the register
>> + * value value to be stored in the register
>> + */
>> +
>> +DATA 4 0x30340004 0x4F400005
>> +/* Clear then set bit30 to ensure exit from DDR retention */
>> +DATA 4 0x30360388 0x40000000
>> +DATA 4 0x30360384 0x40000000
>> +
>> +DATA 4 0x30391000 0x00000002
>> +DATA 4 0x307a0000 0x01040001
>> +DATA 4 0x307a01a0 0x80400003
>> +DATA 4 0x307a01a4 0x00100020
>> +DATA 4 0x307a01a8 0x80100004
>> +DATA 4 0x307a0064 0x00400046
>> +DATA 4 0x307a0490 0x00000001
>> +DATA 4 0x307a00d0 0x00020083
>> +DATA 4 0x307a00d4 0x00690000
>> +DATA 4 0x307a00dc 0x09300004
>> +DATA 4 0x307a00e0 0x04080000
>> +DATA 4 0x307a00e4 0x00100004
>> +DATA 4 0x307a00f4 0x0000033f
>> +DATA 4 0x307a0100 0x09081109
>> +DATA 4 0x307a0104 0x0007020d
>> +DATA 4 0x307a0108 0x03040407
>> +DATA 4 0x307a010c 0x00002006
>> +DATA 4 0x307a0110 0x04020205
>> +DATA 4 0x307a0114 0x03030202
>> +DATA 4 0x307a0120 0x00000803
>> +DATA 4 0x307a0180 0x00800020
>> +DATA 4 0x307a0184 0x02000100
>> +DATA 4 0x307a0190 0x02098204
>> +DATA 4 0x307a0194 0x00030303
>> +DATA 4 0x307a0200 0x00000016
>> +DATA 4 0x307a0204 0x00080808
>> +DATA 4 0x307a0210 0x00000f0f
>> +DATA 4 0x307a0214 0x07070707
>> +DATA 4 0x307a0218 0x0f070707
>> +DATA 4 0x307a0240 0x06000604
>> +DATA 4 0x307a0244 0x00000001
>> +DATA 4 0x30391000 0x00000000
>> +DATA 4 0x30790000 0x17420f40
>> +DATA 4 0x30790004 0x10210100
>> +DATA 4 0x30790010 0x00060807
>> +DATA 4 0x307900b0 0x1010007e
>> +DATA 4 0x3079009c 0x00000b24
>> +DATA 4 0x30790020 0x08080808
>> +DATA 4 0x30790030 0x08080808
>> +DATA 4 0x30790050 0x01000010
>> +DATA 4 0x30790050 0x00000010
>> +
>> +DATA 4 0x307900c0 0x0e407304
>> +DATA 4 0x307900c0 0x0e447304
>> +DATA 4 0x307900c0 0x0e447306
>> +
>> +CHECK_BITS_SET 4 0x307900c4 0x1
>> +
>> +DATA 4 0x307900c0 0x0e407304
>> +
>> +DATA 4 0x30384130 0x00000000
>> +DATA 4 0x30340020 0x00000178
>> +DATA 4 0x30384130 0x00000002
>> +DATA 4 0x30790018 0x0000000f
>> +
>> +CHECK_BITS_SET 4 0x307a0004 0x1
>> diff --git a/board/technexion/pico-imx7d/pico-imx7d.c b/board/technexion/pico-imx7d/pico-imx7d.c
>> new file mode 100644
>> index 0000000..799751d
>> --- /dev/null
>> +++ b/board/technexion/pico-imx7d/pico-imx7d.c
>> @@ -0,0 +1,289 @@
>> +/*
>> + * Copyright (C) 2017 NXP Semiconductors
>> + *
>> + * SPDX-License-Identifier: GPL-2.0+
>> + */
>> +
>> +#include <asm/arch/clock.h>
>> +#include <asm/arch/crm_regs.h>
>> +#include <asm/arch/imx-regs.h>
>> +#include <asm/arch/mx7-pins.h>
>> +#include <asm/arch/sys_proto.h>
>> +#include <asm/gpio.h>
>> +#include <asm/imx-common/iomux-v3.h>
>> +#include <asm/imx-common/mxc_i2c.h>
>> +#include <asm/io.h>
>> +#include <common.h>
>> +#include <fsl_esdhc.h>
>> +#include <i2c.h>
>> +#include <miiphy.h>
>> +#include <mmc.h>
>> +#include <netdev.h>
>> +#include <usb.h>
>> +#include <power/pmic.h>
>> +#include <power/pfuze3000_pmic.h>
>> +#include "../../freescale/common/pfuze.h"
>> +
>> +DECLARE_GLOBAL_DATA_PTR;
>> +
>> +#define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \
>> + PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
>> +
>> +#define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
>> + PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
>> +
>> +#define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
>> +#define ENET_PAD_CTRL_MII (PAD_CTL_DSE_3P3V_32OHM)
>> +
>> +#define ENET_RX_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
>> +
>> +#define I2C_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
>> + PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU100KOHM)
>> +
>> +#ifdef CONFIG_SYS_I2C_MXC
>> +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
>> +/* I2C4 for PMIC */
>> +static struct i2c_pads_info i2c_pad_info4 = {
>> + .scl = {
>> + .i2c_mode = MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL | PC,
>> + .gpio_mode = MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 | PC,
>> + .gp = IMX_GPIO_NR(6, 16),
>> + },
>> + .sda = {
>> + .i2c_mode = MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA | PC,
>> + .gpio_mode = MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17 | PC,
>> + .gp = IMX_GPIO_NR(6, 17),
>> + },
>> +};
>> +#endif
>
> DM_I2C
>
>> +
>> +int dram_init(void)
>> +{
>> + gd->ram_size = PHYS_SDRAM_SIZE;
>> +
>> + return 0;
>> +}
>> +
>> +#ifdef CONFIG_POWER
>> +#define I2C_PMIC 3
>> +int power_init_board(void)
>> +{
>> + struct pmic *p;
>> + int ret;
>> + unsigned int reg, rev_id;
>> +
>> + ret = power_pfuze3000_init(I2C_PMIC);
>> + if (ret)
>> + return ret;
>> +
>> + p = pmic_get("PFUZE3000");
>> + ret = pmic_probe(p);
>> + if (ret)
>> + return ret;
>> +
>> + pmic_reg_read(p, PFUZE3000_DEVICEID, ®);
>> + pmic_reg_read(p, PFUZE3000_REVID, &rev_id);
>> + printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id);
>> +
>> + /* disable Low Power Mode during standby mode */
>> + pmic_reg_read(p, PFUZE3000_LDOGCTL, ®);
>> + reg |= 0x1;
>> + pmic_reg_write(p, PFUZE3000_LDOGCTL, reg);
>> +
>> + /* SW1A/1B mode set to APS/APS */
>> + reg = 0x8;
>> + pmic_reg_write(p, PFUZE3000_SW1AMODE, reg);
>> + pmic_reg_write(p, PFUZE3000_SW1BMODE, reg);
>> +
>> + /* SW1A/1B standby voltage set to 1.025V */
>> + reg = 0xd;
>> + pmic_reg_write(p, PFUZE3000_SW1ASTBY, reg);
>> + pmic_reg_write(p, PFUZE3000_SW1BSTBY, reg);
>> +
>> + /* decrease SW1B normal voltage to 0.975V */
>> + pmic_reg_read(p, PFUZE3000_SW1BVOLT, ®);
>> + reg &= ~0x1f;
>> + reg |= PFUZE3000_SW1AB_SETP(975);
>> + pmic_reg_write(p, PFUZE3000_SW1BVOLT, reg);
>> +
>> + return 0;
>> +}
>> +#endif
>
> DM_PMIC
>
>> +
>> +static iomux_v3_cfg_t const wdog_pads[] = {
>> + MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL),
>> +};
>> +
>> +static iomux_v3_cfg_t const uart5_pads[] = {
>> + MX7D_PAD_I2C4_SCL__UART5_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
>> + MX7D_PAD_I2C4_SDA__UART5_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
>> +};
>> +
>> +static iomux_v3_cfg_t const usdhc3_emmc_pads[] = {
>> + MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> + MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> + MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> + MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> + MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> + MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> + MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> + MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> + MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> + MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> + MX7D_PAD_GPIO1_IO14__GPIO1_IO14 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> +};
>> +
>> +#ifdef CONFIG_FEC_MXC
>> +static iomux_v3_cfg_t const fec1_pads[] = {
>> + MX7D_PAD_SD2_CD_B__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
>> + MX7D_PAD_SD2_WP__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
>> + MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
>> + MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
>> + MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
>> + MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
>> + MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
>> + MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
>> + MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
>> + MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
>> + MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
>> + MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
>> + MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
>> + MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
>> + MX7D_PAD_SD3_STROBE__GPIO6_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
>> + MX7D_PAD_SD3_RESET_B__GPIO6_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
>> +};
>> +
>> +#define FEC1_RST_GPIO IMX_GPIO_NR(6, 11)
>> +
>> +static void setup_iomux_fec(void)
>> +{
>> + imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
>> +
>> + gpio_direction_output(FEC1_RST_GPIO, 0);
>> + udelay(500);
>> + gpio_set_value(FEC1_RST_GPIO, 1);
>> +}
>> +
>> +int board_eth_init(bd_t *bis)
>> +{
>> + setup_iomux_fec();
>> +
>> + return fecmxc_initialize_multi(bis, 0,
>> + CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
>> +}
>> +
>> +static int setup_fec(void)
>> +{
>> + struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
>> + = (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
>> +
>> + /* Use 125M anatop REF_CLK1 for ENET1, clear gpr1[13], gpr1[17] */
>> + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
>> + (IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK |
>> + IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK), 0);
>> +
>> + return set_clk_enet(ENET_125MHz);
>> +}
>
> DM_ETH
>
>> +
>> +int board_phy_config(struct phy_device *phydev)
>> +{
>> + unsigned short val;
>> +
>> + /* To enable AR8035 ouput a 125MHz clk from CLK_25M */
>> + phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
>> + phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
>> + phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
>> +
>> + val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
>> + val &= 0xffe7;
>> + val |= 0x18;
>> + phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
>> +
>> + /* introduce tx clock delay */
>> + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
>> + val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
>> + val |= 0x0100;
>> + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
>> +
>> + if (phydev->drv->config)
>> + phydev->drv->config(phydev);
>> +
>> + return 0;
>> +}
>> +#endif
>> +
>> +static void setup_iomux_uart(void)
>> +{
>> + imx_iomux_v3_setup_multiple_pads(uart5_pads, ARRAY_SIZE(uart5_pads));
>> +}
>> +
>> +static struct fsl_esdhc_cfg usdhc_cfg[1] = {
>> + {USDHC3_BASE_ADDR},
>> +};
>> +
>> +int board_mmc_getcd(struct mmc *mmc)
>> +{
>> + /* Assume uSDHC3 emmc is always present */
>> + return 1;
>> +}
>> +
>> +int board_mmc_init(bd_t *bis)
>> +{
>> + imx_iomux_v3_setup_multiple_pads(
>> + usdhc3_emmc_pads, ARRAY_SIZE(usdhc3_emmc_pads));
>> + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
>> +
>> + return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
>> +}
>
> DM_MMC
>
>> +
>> +int board_early_init_f(void)
>> +{
>> + setup_iomux_uart();
>> +
>> +#ifdef CONFIG_SYS_I2C_MXC
>> + setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info4);
>> +#endif
>> +
>> + return 0;
>> +}
>> +
>> +int board_init(void)
>> +{
>> + /* address of boot parameters */
>> + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
>> +
>> +#ifdef CONFIG_FEC_MXC
>> + setup_fec();
>> +#endif
>> +
>> + return 0;
>> +}
>> +
>> +int board_late_init(void)
>> +{
>> + struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
>> +
>> + imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
>> +
>> + set_wdog_reset(wdog);
>> +
>> + /*
>> + * Do not assert internal WDOG_RESET_B_DEB(controlled by bit 4),
>> + * since we use PMIC_PWRON to reset the board.
>> + */
>> + clrsetbits_le16(&wdog->wcr, 0, 0x10);
>> +
>> + return 0;
>> +}
>> +
>> +int checkboard(void)
>> +{
>> + puts("Board: i.MX7D PICOSOM\n");
>> +
>> + return 0;
>> +}
>> +
>> +int board_usb_phy_mode(int port)
>> +{
>> + return USB_INIT_DEVICE;
>> +}
>> diff --git a/configs/pico-imx7d_defconfig b/configs/pico-imx7d_defconfig
>> new file mode 100644
>> index 0000000..35d4486
>> --- /dev/null
>> +++ b/configs/pico-imx7d_defconfig
>> @@ -0,0 +1,35 @@
>> +CONFIG_ARM=y
>> +CONFIG_ARCH_MX7=y
>> +CONFIG_TARGET_PICO_IMX7D=y
>> +CONFIG_IMX_RDC=y
>> +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/technexion/pico-imx7d/imximage.cfg"
>> +CONFIG_HUSH_PARSER=y
>> +CONFIG_CMD_BOOTZ=y
>> +# CONFIG_CMD_BOOTD is not set
>> +# CONFIG_CMD_IMI is not set
>> +# CONFIG_CMD_IMLS is not set
>> +# CONFIG_CMD_XIMG is not set
>> +# CONFIG_CMD_SETEXPR is not set
>> +CONFIG_CMD_MMC=y
>> +CONFIG_CMD_PART=y
>> +CONFIG_CMD_I2C=y
>> +CONFIG_CMD_GPIO=y
>> +CONFIG_CMD_DHCP=y
>> +CONFIG_CMD_CACHE=y
>> +CONFIG_CMD_EXT2=y
>> +CONFIG_CMD_EXT4=y
>> +CONFIG_CMD_EXT4_WRITE=y
>> +CONFIG_CMD_FAT=y
>> +CONFIG_CMD_USB=y
>> +CONFIG_CMD_USB_MASS_STORAGE=y
>> +CONFIG_USB=y
>> +CONFIG_USB_EHCI_HCD=y
>> +CONFIG_MXC_USB_OTG_HACTIVE=y
>> +CONFIG_USB_STORAGE=y
>> +CONFIG_USB_GADGET=y
>> +CONFIG_CI_UDC=y
>> +CONFIG_USB_GADGET_DOWNLOAD=y
>> +CONFIG_G_DNL_MANUFACTURER="FSL"
>> +CONFIG_G_DNL_VENDOR_NUM=0x0525
>> +CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
>> +CONFIG_OF_LIBFDT=y
>> diff --git a/include/configs/pico-imx7d.h b/include/configs/pico-imx7d.h
>> new file mode 100644
>> index 0000000..d128ede
>> --- /dev/null
>> +++ b/include/configs/pico-imx7d.h
>> @@ -0,0 +1,143 @@
>> +/*
>> + * Copyright (C) 2017 NXP Semiconductors
>> + *
>> + * Configuration settings for the i.MX7D Pico board.
>> + *
>> + * SPDX-License-Identifier: GPL-2.0+
>> + */
>> +
>> +#ifndef __PICO_IMX7D_CONFIG_H
>> +#define __PICO_IMX7D_CONFIG_H
>> +
>> +#include "mx7_common.h"
>> +
>> +#define PHYS_SDRAM_SIZE SZ_1G
>> +
>> +/* Size of malloc() pool */
>> +#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M)
>> +
>> +#define CONFIG_MXC_UART_BASE UART5_IPS_BASE_ADDR
>> +
>> +/* Network */
>> +#define CONFIG_FEC_MXC
>
> Move to defconfig
>
>> +#define CONFIG_MII
>> +#define CONFIG_FEC_XCV_TYPE RGMII
>> +#define CONFIG_ETHPRIME "FEC"
>> +#define CONFIG_FEC_MXC_PHYADDR 1
>> +
>> +#define CONFIG_PHYLIB
>> +#define CONFIG_PHY_ATHEROS
>> +
>> +/* ENET1 */
>> +#define IMX_FEC_BASE ENET_IPS_BASE_ADDR
>
> Can be removed, if dts
>
>> +
>> +/* MMC Config */
>> +#define CONFIG_SYS_FSL_ESDHC_ADDR 0
>> +
>> +#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
>> +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
>> +
>> +#define CONFIG_EXTRA_ENV_SETTINGS \
>> + "script=boot.scr\0" \
>> + "image=zImage\0" \
>> + "console=ttymxc4\0" \
>> + "fdt_high=0xffffffff\0" \
>> + "initrd_high=0xffffffff\0" \
>> + "fdt_file=imx7d-pico.dtb\0" \
>> + "fdt_addr=0x83000000\0" \
>> + "ip_dyn=yes\0" \
>> + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
>> + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
>> + "finduuid=part uuid mmc 0:2 uuid\0" \
>> + "mmcargs=setenv bootargs console=${console},${baudrate} " \
>> + "root=PARTUUID=${uuid} rootwait rw\0" \
>> + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
>> + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
>> + "mmcboot=echo Booting from mmc ...; " \
>> + "run finduuid; " \
>> + "run mmcargs; " \
>> + "if run loadfdt; then " \
>> + "bootz ${loadaddr} - ${fdt_addr}; " \
>> + "else " \
>> + "echo WARN: Cannot load the DT; " \
>> + "fi;\0" \
>> + "netargs=setenv bootargs console=${console},${baudrate} " \
>> + "root=/dev/nfs " \
>> + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
>> + "netboot=echo Booting from net ...; " \
>> + "run netargs; " \
>> + "if test ${ip_dyn} = yes; then " \
>> + "setenv get_cmd dhcp; " \
>> + "else " \
>> + "setenv get_cmd tftp; " \
>> + "fi; " \
>> + "${get_cmd} ${image}; " \
>> + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
>> + "bootz ${loadaddr} - ${fdt_addr}; " \
>> + "else " \
>> + "echo WARN: Cannot load the DT; " \
>> + "fi;\0"
>> +
>> +#define CONFIG_BOOTCOMMAND \
>> + "if mmc rescan; then " \
>> + "if run loadimage; then " \
>> + "run mmcboot; " \
>> + "else run netboot; " \
>> + "fi; " \
>> + "else run netboot; fi"
>> +
>> +#define CONFIG_SYS_MEMTEST_START 0x80000000
>> +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x20000000)
>> +
>> +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
>> +#define CONFIG_SYS_HZ 1000
>> +
>> +/* Physical Memory Map */
>> +#define CONFIG_NR_DRAM_BANKS 1
>> +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
>> +
>> +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
>> +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
>> +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
>> +
>> +#define CONFIG_SYS_INIT_SP_OFFSET \
>> + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
>> +#define CONFIG_SYS_INIT_SP_ADDR \
>> + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
>> +
>> +/* I2C configs */
>> +#define CONFIG_SYS_I2C
>> +#define CONFIG_SYS_I2C_MXC
>> +#define CONFIG_SYS_I2C_MXC_I2C1
>> +#define CONFIG_SYS_I2C_MXC_I2C2
>> +#define CONFIG_SYS_I2C_MXC_I2C3
>> +#define CONFIG_SYS_I2C_MXC_I2C4
>> +#define CONFIG_SYS_I2C_SPEED 100000
>
> Can be removed, if dts
>
>> +
>> +/* PMIC */
>> +#define CONFIG_POWER
>> +#define CONFIG_POWER_I2C
>> +#define CONFIG_POWER_PFUZE3000
>> +#define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08
>
> Can be removed, if dts
>
>> +
>> +/* FLASH and environment organization */
>> +#define CONFIG_ENV_SIZE SZ_8K
>> +#define CONFIG_ENV_IS_IN_MMC
>> +
>> +#define CONFIG_ENV_OFFSET (8 * SZ_64K)
>> +#define CONFIG_SYS_FSL_USDHC_NUM 2
>> +
>> +#define CONFIG_SYS_MMC_ENV_DEV 0
>> +#define CONFIG_SYS_MMC_ENV_PART 0
>> +
>> +/* USB Configs */
>> +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
>> +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
>> +#define CONFIG_MXC_USB_FLAGS 0
>> +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
>> +
>> +#define CONFIG_IMX_THERMAL
>
> Move to defconfig
>
> thanks!
>
--
=====================================================================
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
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