[U-Boot] [PATCH 32/33] dts: rk3399: change the maximum eMMC clock frequency to 150MHz

[Ziyuan Xu]

The rockchip mmc controllers don't support _the _odd__ divider,
otherwise probably cause unpredictable error.

The driver originally select gpll(594M) as the clock source, and we set
div to 3 at 200MHz. We have to change the maximum eMMC clock frequency
to 150MHz in U-Boot stage, so that the div will be 4.

Signed-off-by: Ziyuan Xu <xzy.xu at rock-chips.com>
---

 arch/arm/dts/rk3399.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/dts/rk3399.dtsi b/arch/arm/dts/rk3399.dtsi
index f3d3f53..b2122b6 100644
--- a/arch/arm/dts/rk3399.dtsi
+++ b/arch/arm/dts/rk3399.dtsi
@@ -283,7 +283,7 @@
 		arasan,soc-ctl-syscon = <&grf>;
 		assigned-clocks = <&cru SCLK_EMMC>;
 		assigned-clock-rates = <200000000>;
-		max-frequency = <200000000>;
+		max-frequency = <150000000>;
 		clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
 		clock-names = "clk_xin", "clk_ahb";
 		clock-output-names = "emmc_cardclock";
-- 
2.7.4