[U-Boot] [PATCH v2 2/3] rockchip: clock: rk3036: some fix according TRM
Simon Glass
sjg at chromium.org
Wed May 17 01:38:40 UTC 2017
On 15 May 2017 at 06:52, Kever Yang <kever.yang at rock-chips.com> wrote:
> - hclk/pclk_div range should use '<=' instead of '<'
> - use GPLL for pd_bus clock source
> - pd_bus HCLK/PCLK clock rate should not bigger than ACLK
>
> Signed-off-by: Kever Yang <kever.yang at rock-chips.com>
> ---
>
> Changes in v2: None
>
> arch/arm/include/asm/arch-rockchip/cru_rk3036.h | 6 +++---
> drivers/clk/rockchip/clk_rk3036.c | 18 +++++++++---------
> 2 files changed, 12 insertions(+), 12 deletions(-)
Reviewed-by: Simon Glass <sjg at chromium.org>
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