[U-Boot] Very slow mtest on i.MX6UL over dual-die DDR3 (two chip selects)

[Palacios, Hector]

Hi Fabio,

On Wed, 17 May 2017 00:34, Fabio Estevam wrote:
> Hi Hector,
> 
> On Tue, May 16, 2017 at 1:15 PM, Palacios, Hector
> <Hector.Palacios at digi.com> wrote:
>> Greetings,
>> 
>> I'm adding support to a 1GiB DDR3 chip that internally has two dies. I
> have configured the i.MX6UL memory controller for using two chip selects
> and assigned 512MiB to each. Although the RAM seems to work fine I'm
> experiencing extremely slow performance compared to a similar 1GiB chip
> with only one die (one chip select).
>> 
>> Testing one mtest loop over the first 496MiB takes:
>>  - 5s on the single die chip
>>  - 1m 16s on the dual die chip
>> I have run different memory benchmark tools in Linux like
> https://github.com/bingmann/pmbw.git and both memories perform similarly,
> but for some reason I see this weird behavior in U-Boot (v2015.04) with
> 'mtest'.
>> The CONFIG_SYS_MEMTEST_START and CONFIG_SYS_MEMTEST_END are defined within secure limits and
>> 'mtest' is not failing... it's just very slow.
>> 
>> Am I missing something obvious?
> 
> It is hard to tell without seeing your code.
> 
> What about adding your mx6ul board support upstream?

The code is on Github [1] (well, not the dual-die DDR3 yet) but there isn't much to see for this issue other than:

#define CONFIG_CMD_MEMTEST
#define CONFIG_SYS_MEMTEST_START	0x80000000
#define CONFIG_SYS_MEMTEST_END	0x9fffffff	/* 512 MiB */

For the dual-die DDR3, I apply the following change to the board .cfg file:

diff --git a/board/digi/ccimx6ul/imximage1GB.cfg b/board/digi/ccimx6ul/imximage1GB.cfg
index f72888bc2bfe..952458d45970 100644
--- a/board/digi/ccimx6ul/imximage1GB.cfg
+++ b/board/digi/ccimx6ul/imximage1GB.cfg
@@ -115,8 +115,8 @@ DATA 4 0x021B0018 0x00201740
 DATA 4 0x021B001C 0x00008000
 DATA 4 0x021B002C 0x000026D2
 DATA 4 0x021B0030 0x008F1023
-DATA 4 0x021B0040 0x0000005F
-DATA 4 0x021B0000 0x85180000
+DATA 4 0x021B0040 0x0000004F
+DATA 4 0x021B0000 0xC5180000
 
 /* Mode registers writes for CS0 */
 DATA 4 0x021B001C 0x02088032
@@ -125,6 +125,13 @@ DATA 4 0x021B001C 0x00048031
 DATA 4 0x021B001C 0x15208030
 DATA 4 0x021B001C 0x04008040
 
+/* Mode registers writes for CS1 */
+DATA 4 0x021B001C 0x0208803A
+DATA 4 0x021B001C 0x0000803B
+DATA 4 0x021B001C 0x00048039
+DATA 4 0x021B001C 0x15208038
+DATA 4 0x021B001C 0x04008048
+
 /* Final DDR setup */
 DATA 4 0x021B0020 0x00000800
 DATA 4 0x021B0818 0x00000227

So basically it's enabling the CS1 of the MMDC, and reducing the CS0_END to half the memory per chip select.

	[1] https://github.com/digi-embedded/u-boot


Thanks,
--
Héctor Palacios