[U-Boot] [PATCH 1/2] x86: ich6_gpio: Add use-lvl-write-cache for I/O access mode

[Bin Meng]

On Mon, May 15, 2017 at 11:02 AM, Simon Glass <sjg at chromium.org> wrote:
> On 7 May 2017 at 20:52, Bin Meng <bmeng.cn at gmail.com> wrote:
>> Add a device-tree property use-lvl-write-cache that will cause
>> writes to lvl to be cached instead of read from lvl before each
>> write. This is required on some platforms that have the register
>> implemented as dual read/write (such as Baytrail).
>>
>> Prior to this fix the blue USB port on the Minnowboard Max was
>> unusable since USB_HOST_EN0 was set high then immediately set
>> low when USB_HOST_EN1 was written.
>>
>> This also resolves the 'gpio clear | set' command warning like:
>>   "Warning: value of pin is still 0"
>>
>> Signed-off-by: George McCollister <george.mccollister at gmail.com>
>> <rebased on latest origin/master, fixed all baytrail boards>
>> Signed-off-by: Bin Meng <bmeng.cn at gmail.com>
>>
>> ---
>>
>>  arch/x86/dts/bayleybay.dts                    |  6 ++++++
>>  arch/x86/dts/baytrail_som-db5800-som-6867.dts |  6 ++++++
>>  arch/x86/dts/conga-qeval20-qa3-e3845.dts      |  6 ++++++
>>  arch/x86/dts/dfi-bt700.dtsi                   |  6 ++++++
>>  arch/x86/dts/minnowmax.dts                    |  6 ++++++
>>  drivers/gpio/intel_ich6_gpio.c                | 30 ++++++++++++++++++++++-----
>>  6 files changed, 55 insertions(+), 5 deletions(-)
>
> Reviewed-by: Simon Glass <sjg at chromium.org>
>
> I think we need a binding file for intel,ich6-gpio.

Yes!

applied to u-boot-x86, thanks!