[U-Boot] Very slow mtest on i.MX6UL over dual-die DDR3 (two chip selects)

[Fabio Estevam]

Hi Hector,

On Thu, May 18, 2017 at 11:43 AM, Hector Palacios
<hector.palacios at digi.com> wrote:

> In case I wasn't clear, I don't have any memory mapping problems. I have one single
> DDR chip, which internally uses two dies and two chip selects. Setting
> CONFIG_NR_DRAM_BANKS to 1 (and full size) or 2 (and half size) in U-Boot doesn't make
> any difference in terms of performance.

Ok, thanks for the clarification.

> Additional investigation showed the following:
>
> NXP DDR stress test takes the same time to complete (successfully) in both variants
> (single-die with one chip select and 1GB density per CS, and dual-die with two chip
> select and 512MB per CS)
>
> The slow memory access is global in U-Boot, not limited to 'mtest' command. A memory
> copy command for 256M (time cp.l 90000000 80000000 4000000) takes:
> - 1.304s on the single-die DDR3
> - 15.866 seconds on the dual-die DDR3
>
> Note that both data/instuction cache are ON on both devices, and that I'm only
> exercising the lower memory (only CS0 on the dual-die chip) to avoid potential issues
> or delays between changing from CS0 to CS1.
>
> I also verified that configuring the MMDC0 for using only one CS on the dual-die DDR3
> chip (and only half the size), does not help. This DDR is still performing slowly in
> U-Boot, but I can't find the reason why.

I got very slow performance with MX6UL when U-Boot is loaded via
serial download mode.

This gets fixed by setting the SMP bit:
https://patchwork.ozlabs.org/patch/747074/

Looks like your issue is not related though.

Another experiment: could you try the same tests running on U-Boot 2017.05?