[U-Boot] [PATCH 09/26] dm: video: tegra124: Convert to livetree

[Simon Glass]

Update these drivers to support a live device tree.

Signed-off-by: Simon Glass <sjg at chromium.org>
---

 drivers/video/tegra124/display.c |  8 +++-----
 drivers/video/tegra124/dp.c      |  3 +--
 drivers/video/tegra124/sor.c     | 25 +++++++------------------
 3 files changed, 11 insertions(+), 25 deletions(-)

diff --git a/drivers/video/tegra124/display.c b/drivers/video/tegra124/display.c
index 47752b27f1..4164fa1bd9 100644
--- a/drivers/video/tegra124/display.c
+++ b/drivers/video/tegra124/display.c
@@ -12,7 +12,6 @@
 #include <errno.h>
 #include <display.h>
 #include <edid.h>
-#include <fdtdec.h>
 #include <lcd.h>
 #include <video.h>
 #include <asm/gpio.h>
@@ -334,7 +333,6 @@ static int display_init(struct udevice *dev, void *lcdbase,
 {
 	struct display_plat *disp_uc_plat;
 	struct dc_ctlr *dc_ctlr;
-	const void *blob = gd->fdt_blob;
 	struct udevice *dp_dev;
 	const int href_to_sync = 1, vref_to_sync = 1;
 	int panel_bpp = 18;	/* default 18 bits per pixel */
@@ -363,9 +361,8 @@ static int display_init(struct udevice *dev, void *lcdbase,
 		return ret;
 	}
 
-	dc_ctlr = (struct dc_ctlr *)fdtdec_get_addr(blob, dev_of_offset(dev),
-						    "reg");
-	if (fdtdec_decode_display_timing(blob, dev_of_offset(dev), 0, timing)) {
+	dc_ctlr = (struct dc_ctlr *)dev_read_addr(dev);
+	if (ofnode_decode_display_timing(dev_ofnode(dev), 0, timing)) {
 		debug("%s: Failed to decode display timing\n", __func__);
 		return -EINVAL;
 	}
@@ -416,6 +413,7 @@ static int display_init(struct udevice *dev, void *lcdbase,
 		debug("dc: failed to update window\n");
 		return ret;
 	}
+	debug("%s: ready\n", __func__);
 
 	return 0;
 }
diff --git a/drivers/video/tegra124/dp.c b/drivers/video/tegra124/dp.c
index c38b3e5335..95d743d0f4 100644
--- a/drivers/video/tegra124/dp.c
+++ b/drivers/video/tegra124/dp.c
@@ -10,7 +10,6 @@
 #include <dm.h>
 #include <div64.h>
 #include <errno.h>
-#include <fdtdec.h>
 #include <video_bridge.h>
 #include <asm/io.h>
 #include <asm/arch-tegra/dc.h>
@@ -1572,7 +1571,7 @@ static int tegra_dp_ofdata_to_platdata(struct udevice *dev)
 {
 	struct tegra_dp_plat *plat = dev_get_platdata(dev);
 
-	plat->base = devfdt_get_addr(dev);
+	plat->base = dev_read_addr(dev);
 
 	return 0;
 }
diff --git a/drivers/video/tegra124/sor.c b/drivers/video/tegra124/sor.c
index 5e4140ff53..1f5e572bda 100644
--- a/drivers/video/tegra124/sor.c
+++ b/drivers/video/tegra124/sor.c
@@ -7,9 +7,9 @@
 #include <common.h>
 #include <dm.h>
 #include <errno.h>
-#include <fdtdec.h>
 #include <malloc.h>
 #include <panel.h>
+#include <syscon.h>
 #include <video_bridge.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
@@ -750,15 +750,12 @@ int tegra_dc_sor_attach(struct udevice *dc_dev, struct udevice *dev,
 			const struct display_timing *timing)
 {
 	struct tegra_dc_sor_data *sor = dev_get_priv(dev);
-	const void *blob = gd->fdt_blob;
 	struct dc_ctlr *disp_ctrl;
 	u32 reg_val;
-	int node;
 
 	/* Use the first display controller */
 	debug("%s\n", __func__);
-	node = dev_of_offset(dc_dev);
-	disp_ctrl = (struct dc_ctlr *)fdtdec_get_addr(blob, node, "reg");
+	disp_ctrl = (struct dc_ctlr *)dev_read_addr(dc_dev);
 
 	tegra_dc_sor_enable_dc(disp_ctrl);
 	tegra_dc_sor_config_panel(sor, 0, link_cfg, timing);
@@ -965,16 +962,13 @@ int tegra_dc_sor_detach(struct udevice *dc_dev, struct udevice *dev)
 {
 	struct tegra_dc_sor_data *sor = dev_get_priv(dev);
 	int dc_reg_ctx[DC_REG_SAVE_SPACE];
-	const void *blob = gd->fdt_blob;
 	struct dc_ctlr *disp_ctrl;
 	unsigned long dc_int_mask;
-	int node;
 	int ret;
 
 	debug("%s\n", __func__);
 	/* Use the first display controller */
-	node = dev_of_offset(dc_dev);
-	disp_ctrl = (struct dc_ctlr *)fdtdec_get_addr(blob, node, "reg");
+	disp_ctrl = (struct dc_ctlr *)dev_read_addr(dev);
 
 	/* Sleep mode */
 	tegra_sor_writel(sor, SUPER_STATE1, SUPER_STATE1_ASY_HEAD_OP_SLEEP |
@@ -1041,18 +1035,13 @@ static int tegra_sor_set_backlight(struct udevice *dev, int percent)
 static int tegra_sor_ofdata_to_platdata(struct udevice *dev)
 {
 	struct tegra_dc_sor_data *priv = dev_get_priv(dev);
-	const void *blob = gd->fdt_blob;
-	int node;
 	int ret;
 
-	priv->base = (void *)fdtdec_get_addr(blob, dev_of_offset(dev), "reg");
+	priv->base = (void *)dev_read_addr(dev);
 
-	node = fdtdec_next_compatible(blob, 0, COMPAT_NVIDIA_TEGRA124_PMC);
-	if (node < 0) {
-		debug("%s: Cannot find PMC\n", __func__);
-		return -ENOENT;
-	}
-	priv->pmc_base = (void *)fdtdec_get_addr(blob, node, "reg");
+	priv->pmc_base = (void *)syscon_get_first_range(TEGRA_SYSCON_PMC);
+	if (IS_ERR(priv->pmc_base))
+		return PTR_ERR(priv->pmc_base);
 
 	ret = uclass_get_device_by_phandle(UCLASS_PANEL, dev, "nvidia,panel",
 					   &priv->panel);
-- 
2.13.0.303.g4ebf302169-goog