[U-Boot] [RESEND PATCH v2 4/5] net: pch_gbe: Add cache maintenance

[Joe Hershberger]

On Sun, Apr 30, 2017 at 2:57 PM, Daniel Schwierzeck
<daniel.schwierzeck at gmail.com> wrote:
> From: Paul Burton <paul.burton at imgtec.com>
>
> On MIPS systems DMA isn't coherent with the CPU caches unless an IOCU is
> present. When there is no IOCU we need to writeback or invalidate the
> data caches at appropriate points. Perform this cache maintenance in
> the pch_gbe driver which is used on the MIPS Boston development board.
>
> Signed-off-by: Paul Burton <paul.burton at imgtec.com>
> Reviewed-by: Bin Meng <bmeng.cn at gmail.com>
> Tested-by: Bin Meng <bmeng.cn at gmail.com>
> Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck at gmail.com>

Acked-by: Joe Hershberger <joe.hershberger at ni.com>